From ffe2a503b06cc300e25c1dfc00c85a2240cf97d7 Mon Sep 17 00:00:00 2001
From: Changbin Du <changbin.du@intel.com>
Date: Mon, 30 Oct 2017 14:19:15 +0800
Subject: [PATCH] drm/i915/gvt: Reduce rcs mocs switch latency
Git-commit: ffe2a503b06cc300e25c1dfc00c85a2240cf97d7
Patch-mainline: v4.16-rc1
References: FATE#322643 bsc#1055900
Use I915_WRITE_FW instead of I915_WRITE to reduce overhead.
The overall mmio switch latency lowers from ~600us to ~180us.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/gpu/drm/i915/gvt/render.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -209,7 +209,7 @@ static void load_mocs(struct intel_vgpu
offset.reg = regs[ring_id];
for (i = 0; i < 64; i++) {
gen9_render_mocs[ring_id][i] = I915_READ_FW(offset);
- I915_WRITE(offset, vgpu_vreg(vgpu, offset));
+ I915_WRITE_FW(offset, vgpu_vreg(vgpu, offset));
offset.reg += 4;
}