From: Yue Hin Lau <Yuehin.Lau@amd.com>
Date: Thu, 28 Sep 2017 16:09:56 -0400
Subject: drm/amd/display: Making hubp1_program_surface_config public
Git-commit: e4b3b5ccd9835bafab67851a7cc759c9250a8a9d
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 9 +++++++++
2 files changed, 11 insertions(+), 1 deletion(-)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
@@ -407,7 +407,7 @@ void hubp1_dcc_control(struct mem_input
PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
}
-static void hubp1_program_surface_config(
+void hubp1_program_surface_config(
struct mem_input *mem_input,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
@@ -970,3 +970,4 @@ void dcn10_mem_input_construct(
mi->base.mpcc_id = 0xf;
}
+
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
@@ -591,6 +591,15 @@ struct dcn10_mem_input {
const struct dcn_mi_mask *mi_mask;
};
+void hubp1_program_surface_config(
+ struct mem_input *mem_input,
+ enum surface_pixel_format format,
+ union dc_tiling_info *tiling_info,
+ union plane_size *plane_size,
+ enum dc_rotation_angle rotation,
+ struct dc_plane_dcc_param *dcc,
+ bool horizontal_mirror);
+
void hubp1_program_deadline(
struct mem_input *mem_input,
struct _vcs_dpi_display_dlg_regs_st *dlg_attr,