From d1d247543c5626eac1064aafd0a35c231828c211 Mon Sep 17 00:00:00 2001
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Date: Tue, 15 Aug 2017 16:16:50 -0700
Subject: [PATCH] drm/i915/cnl: WaDisableEnhancedSBEVertexCaching
Git-commit: d1d247543c5626eac1064aafd0a35c231828c211
Patch-mainline: v4.15-rc1
References: FATE#322643 bsc#1055900
WA forTDS handle reallocation getting dropped by SDE,
which may result in PS attribute corruption.
Disable enhanced SBE vertex caching in COMMON_SLICE_CHICKEN2 offset.
V2: Make it until B0 as spec tells. (by Mika).
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170815231651.975-3-rodrigo.vivi@intel.com
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++
1 file changed, 5 insertions(+)
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1077,6 +1077,11 @@ static int cnl_init_workarounds(struct i
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+ /* WaDisableEnhancedSBEVertexCaching:cnl (pre-prod) */
+ if (IS_CNL_REVID(dev_priv, 0, CNL_REVID_B0))
+ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+ GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
+
/* WaInPlaceDecompressionHang:cnl */
WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);