From: Thomas Bogendoerfer <tbogendoerfer@suse.de>
Subject: mlx5 PPC ringsize workaround
Patch-mainline: never, workaround from Mellanox OFED
References: bsc#1173432
Looks like PPC64 iommu code base in SLE15-SP1 is missing something
called Dynamic DMA windows, which leads to inefficient dma mappings
and running out of iommu slots. A workaround is to reduce the number
of RX ring entires. This hack is implemented in Mellanox OFED driver
and this patch brings it to our code base.
Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
---
drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 6 ++++++
1 file changed, 6 insertions(+)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
@@ -203,6 +203,12 @@ void mlx5e_init_rq_type_params(struct ml
MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
+#ifdef CONFIG_PPC64
+ /* If ddw is not enabled, set ring size to 512 */
+ if (!get_dma_offset(&mdev->pdev->dev) && (params->log_rq_mtu_frames > 9))
+ params->log_rq_mtu_frames = 9;
+#endif
+
mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?