From: Martin Habets <habetsm.xilinx@gmail.com>
Date: Thu, 27 Jul 2023 11:41:32 +0100
Subject: sfc: Cleanups in io.h
Patch-mainline: v6.6-rc1
Git-commit: b0d1fe9bcdc66406dcc650ec0b750bd3c2ce2005
References: jsc#PED-6894
Most of the Falcon locking description does not apply to EF10.
Signed-off-by: Martin Habets <habetsm.xilinx@gmail.com>
Acked-by: Edward Cree <ecree.xilinx@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
---
drivers/net/ethernet/sfc/io.h | 84 ++++-------------------------------------
drivers/net/ethernet/sfc/nic.c | 5 --
2 files changed, 9 insertions(+), 80 deletions(-)
--- a/drivers/net/ethernet/sfc/io.h
+++ b/drivers/net/ethernet/sfc/io.h
@@ -17,46 +17,22 @@
*
**************************************************************************
*
- * Notes on locking strategy for the Falcon architecture:
- *
- * Many CSRs are very wide and cannot be read or written atomically.
- * Writes from the host are buffered by the Bus Interface Unit (BIU)
- * up to 128 bits. Whenever the host writes part of such a register,
- * the BIU collects the written value and does not write to the
- * underlying register until all 4 dwords have been written. A
- * similar buffering scheme applies to host access to the NIC's 64-bit
- * SRAM.
- *
- * Writes to different CSRs and 64-bit SRAM words must be serialised,
- * since interleaved access can result in lost writes. We use
- * efx_nic::biu_lock for this.
- *
- * We also serialise reads from 128-bit CSRs and SRAM with the same
- * spinlock. This may not be necessary, but it doesn't really matter
- * as there are no such reads on the fast path.
+ * The EF10 architecture exposes very few registers to the host and
+ * most of them are only 32 bits wide. The only exceptions are the MC
+ * doorbell register pair, which has its own latching, and
+ * TX_DESC_UPD.
*
- * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
- * 128-bit but are special-cased in the BIU to avoid the need for
- * locking in the host:
+ * The TX_DESC_UPD DMA descriptor pointer is 128-bits but is a special
+ * case in the BIU to avoid the need for locking in the host:
*
- * - They are write-only.
- * - The semantics of writing to these registers are such that
+ * - It is write-only.
+ * - The semantics of writing to this register is such that
* replacing the low 96 bits with zero does not affect functionality.
- * - If the host writes to the last dword address of such a register
+ * - If the host writes to the last dword address of the register
* (i.e. the high 32 bits) the underlying register will always be
* written. If the collector and the current write together do not
* provide values for all 128 bits of the register, the low 96 bits
* will be written as zero.
- * - If the host writes to the address of any other part of such a
- * register while the collector already holds values for some other
- * register, the write is discarded and the collector maintains its
- * current state.
- *
- * The EF10 architecture exposes very few registers to the host and
- * most of them are only 32 bits wide. The only exceptions are the MC
- * doorbell register pair, which has its own latching, and
- * TX_DESC_UPD, which works in a similar way to the Falcon
- * architecture.
*/
#if BITS_PER_LONG == 64
@@ -125,27 +101,6 @@ static inline void efx_writeo(struct efx
spin_unlock_irqrestore(&efx->biu_lock, flags);
}
-/* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
-static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
- const efx_qword_t *value, unsigned int index)
-{
- unsigned int addr = index * sizeof(*value);
- unsigned long flags __attribute__ ((unused));
-
- netif_vdbg(efx, hw, efx->net_dev,
- "writing SRAM address %x with " EFX_QWORD_FMT "\n",
- addr, EFX_QWORD_VAL(*value));
-
- spin_lock_irqsave(&efx->biu_lock, flags);
-#ifdef EFX_USE_QWORD_IO
- __raw_writeq((__force u64)value->u64[0], membase + addr);
-#else
- __raw_writel((__force u32)value->u32[0], membase + addr);
- __raw_writel((__force u32)value->u32[1], membase + addr + 4);
-#endif
- spin_unlock_irqrestore(&efx->biu_lock, flags);
-}
-
/* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
static inline void efx_writed(struct efx_nic *efx, const efx_dword_t *value,
unsigned int reg)
@@ -176,27 +131,6 @@ static inline void efx_reado(struct efx_
EFX_OWORD_VAL(*value));
}
-/* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
-static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
- efx_qword_t *value, unsigned int index)
-{
- unsigned int addr = index * sizeof(*value);
- unsigned long flags __attribute__ ((unused));
-
- spin_lock_irqsave(&efx->biu_lock, flags);
-#ifdef EFX_USE_QWORD_IO
- value->u64[0] = (__force __le64)__raw_readq(membase + addr);
-#else
- value->u32[0] = (__force __le32)__raw_readl(membase + addr);
- value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
-#endif
- spin_unlock_irqrestore(&efx->biu_lock, flags);
-
- netif_vdbg(efx, hw, efx->net_dev,
- "read from SRAM address %x, got "EFX_QWORD_FMT"\n",
- addr, EFX_QWORD_VAL(*value));
-}
-
/* Read a 32-bit CSR or SRAM */
static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,
unsigned int reg)
--- a/drivers/net/ethernet/sfc/nic.c
+++ b/drivers/net/ethernet/sfc/nic.c
@@ -272,11 +272,6 @@ void efx_nic_get_regs(struct efx_nic *ef
case 4: /* 32-bit SRAM */
efx_readd(efx, buf, table->offset + 4 * i);
break;
- case 8: /* 64-bit SRAM */
- efx_sram_readq(efx,
- efx->membase + table->offset,
- buf, i);
- break;
case 16: /* 128-bit-readable register */
efx_reado_table(efx, buf, table->offset, i);
break;