From d4d03be699f613df67580d6c846f7261bfab76f9 Mon Sep 17 00:00:00 2001
From: Lijo Lazar <lijo.lazar@amd.com>
Date: Tue, 29 Nov 2022 14:00:37 +0530
Subject: drm/amdgpu: Use mask for active clusters
Git-commit: 7a1efad04c210594069c4ab9f9c25039cd6915e4
Patch-mainline: v6.5-rc1
References: jsc#PED-3527 jsc#PED-5475 jsc#PED-6068 jsc#PED-6070 jsc#PED-6116 jsc#PED-6120 jsc#PED-5065 jsc#PED-5477 jsc#PED-5511 jsc#PED-6041 jsc#PED-6069 jsc#PED-6071
Use a mask of available active clusters instead of using only the number
of active clusters.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +-
.../drm/amd/amdgpu/aqua_vanjaram_reg_init.c | 13 +++--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +-
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 56 ++++++++++++-------
4 files changed, 49 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3858d29baef1..279057ec7a0b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1070,7 +1070,8 @@ struct amdgpu_device {
bool job_hang;
bool dc_enabled;
- uint32_t num_aid;
+ /* Mask of active clusters */
+ uint32_t aid_mask;
};
static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c
index 6f7226b5d446..0d7bc212def1 100644
--- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c
@@ -358,25 +358,26 @@ static int aqua_vanjaram_xcp_mgr_init(struct amdgpu_device *adev)
int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev)
{
u32 inst_mask = adev->sdma.sdma_mask;
- int ret;
+ int ret, i, num_inst;
/* generally 1 AID supports 4 instances */
adev->sdma.num_inst_per_aid = 4;
adev->sdma.num_instances = NUM_SDMA(adev->sdma.sdma_mask);
- adev->num_aid = 1;
+ adev->aid_mask = i = 1;
inst_mask >>= adev->sdma.num_inst_per_aid;
for (const u32 mask = (1 << adev->sdma.num_inst_per_aid) - 1; inst_mask;
- inst_mask >>= adev->sdma.num_inst_per_aid) {
+ inst_mask >>= adev->sdma.num_inst_per_aid, ++i) {
if ((inst_mask & mask) == mask)
- adev->num_aid++;
+ adev->aid_mask |= (1 << i);
}
+ num_inst = hweight32(adev->aid_mask);
adev->vcn.num_inst_per_aid = 1;
- adev->vcn.num_vcn_inst = adev->vcn.num_inst_per_aid * adev->num_aid;
+ adev->vcn.num_vcn_inst = adev->vcn.num_inst_per_aid * num_inst;
adev->jpeg.num_inst_per_aid = 1;
- adev->jpeg.num_jpeg_inst = adev->jpeg.num_inst_per_aid * adev->num_aid;
+ adev->jpeg.num_jpeg_inst = adev->jpeg.num_inst_per_aid * num_inst;
ret = aqua_vanjaram_xcp_mgr_init(adev);
if (ret)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 0792c48fe347..b3f64f2f306d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1674,6 +1674,7 @@ static int gmc_v9_0_sw_init(void *handle)
{
int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ unsigned long inst_mask = adev->aid_mask;
adev->gfxhub.funcs->init(adev);
@@ -1757,7 +1758,9 @@ static int gmc_v9_0_sw_init(void *handle)
case IP_VERSION(9, 4, 3):
bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0),
NUM_XCC(adev->gfx.xcc_mask));
- bitmap_set(adev->vmhubs_mask, AMDGPU_MMHUB0(0), adev->num_aid);
+
+ inst_mask <<= AMDGPU_MMHUB0(0);
+ bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32);
amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
index 6f469b9aa9a0..a530e2a3cc28 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
@@ -54,9 +54,11 @@ static void mmhub_v1_8_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmi
uint64_t page_table_base)
{
struct amdgpu_vmhub *hub;
+ u32 inst_mask;
int i;
- for (i = 0; i < adev->num_aid; i++) {
+ inst_mask = adev->aid_mask;
+ for_each_inst(i, inst_mask) {
hub = &adev->vmhub[AMDGPU_MMHUB0(i)];
WREG32_SOC15_OFFSET(MMHUB, i,
regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
@@ -73,6 +75,7 @@ static void mmhub_v1_8_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmi
static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev)
{
uint64_t pt_base;
+ u32 inst_mask;
int i;
if (adev->gmc.pdb0_bo)
@@ -85,7 +88,8 @@ static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev)
/* If use GART for FB translation, vmid0 page table covers both
* vram and system memory (gart)
*/
- for (i = 0; i < adev->num_aid; i++) {
+ inst_mask = adev->aid_mask;
+ for_each_inst(i, inst_mask) {
if (adev->gmc.pdb0_bo) {
WREG32_SOC15(MMHUB, i,
regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
@@ -121,11 +125,12 @@ static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev)
static void mmhub_v1_8_init_system_aperture_regs(struct amdgpu_device *adev)
{
+ uint32_t tmp, inst_mask;
uint64_t value;
- uint32_t tmp;
int i;
- for (i = 0; i < adev->num_aid; i++) {
+ inst_mask = adev->aid_mask;
+ for_each_inst(i, inst_mask) {
/* Program the AGP BAR */
WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BASE, 0);
WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BOT,
@@ -183,11 +188,12 @@ static void mmhub_v1_8_init_system_aperture_regs(struct amdgpu_device *adev)
static void mmhub_v1_8_init_tlb_regs(struct amdgpu_device *adev)
{
- uint32_t tmp;
+ uint32_t tmp, inst_mask;
int i;
/* Setup TLB control */
- for (i = 0; i < adev->num_aid; i++) {
+ inst_mask = adev->aid_mask;
+ for_each_inst(i, inst_mask) {
tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
@@ -208,14 +214,15 @@ static void mmhub_v1_8_init_tlb_regs(struct amdgpu_device *adev)
static void mmhub_v1_8_init_cache_regs(struct amdgpu_device *adev)
{
- uint32_t tmp;
+ uint32_t tmp, inst_mask;
int i;
if (amdgpu_sriov_vf(adev))
return;
/* Setup L2 cache */
- for (i = 0; i < adev->num_aid; i++) {
+ inst_mask = adev->aid_mask;
+ for_each_inst(i, inst_mask) {
tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
@@ -267,10 +274,11 @@ static void mmhub_v1_8_init_cache_regs(struct amdgpu_device *adev)
static void mmhub_v1_8_enable_system_domain(struct amdgpu_device *adev)
{
- uint32_t tmp;
+ uint32_t tmp, inst_mask;
int i;
- for (i = 0; i < adev->num_aid; i++) {
+ inst_mask = adev->aid_mask;
+ for_each_inst(i, inst_mask) {
tmp = RREG32_SOC15(MMHUB, i, regVM_CONTEXT0_CNTL);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
@@ -286,12 +294,14 @@ static void mmhub_v1_8_enable_system_domain(struct amdgpu_device *adev)
static void mmhub_v1_8_disable_identity_aperture(struct amdgpu_device *adev)
{
+ u32 inst_mask;
int i;
if (amdgpu_sriov_vf(adev))
return;
- for (i = 0; i < adev->num_aid; i++) {
+ inst_mask = adev->aid_mask;
+ for_each_inst(i, inst_mask) {
WREG32_SOC15(MMHUB, i,
regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
0XFFFFFFFF);
@@ -317,7 +327,7 @@ static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
{
struct amdgpu_vmhub *hub;
unsigned num_level, block_size;
- uint32_t tmp;
+ uint32_t tmp, inst_mask;
int i, j;
num_level = adev->vm_manager.num_level;
@@ -327,7 +337,8 @@ static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
else
block_size -= 9;
- for (j = 0; j < adev->num_aid; j++) {
+ inst_mask = adev->aid_mask;
+ for_each_inst(j, inst_mask) {
hub = &adev->vmhub[AMDGPU_MMHUB0(j)];
for (i = 0; i <= 14; i++) {
tmp = RREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT1_CNTL,
@@ -382,9 +393,10 @@ static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
static void mmhub_v1_8_program_invalidation(struct amdgpu_device *adev)
{
struct amdgpu_vmhub *hub;
- unsigned i, j;
+ u32 i, j, inst_mask;
- for (j = 0; j < adev->num_aid; j++) {
+ inst_mask = adev->aid_mask;
+ for_each_inst(j, inst_mask) {
hub = &adev->vmhub[AMDGPU_MMHUB0(j)];
for (i = 0; i < 18; ++i) {
WREG32_SOC15_OFFSET(MMHUB, j,
@@ -429,10 +441,11 @@ static void mmhub_v1_8_gart_disable(struct amdgpu_device *adev)
{
struct amdgpu_vmhub *hub;
u32 tmp;
- u32 i, j;
+ u32 i, j, inst_mask;
/* Disable all tables */
- for (j = 0; j < adev->num_aid; j++) {
+ inst_mask = adev->aid_mask;
+ for_each_inst(j, inst_mask) {
hub = &adev->vmhub[AMDGPU_MMHUB0(j)];
for (i = 0; i < 16; i++)
WREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT0_CNTL,
@@ -465,13 +478,14 @@ static void mmhub_v1_8_gart_disable(struct amdgpu_device *adev)
*/
static void mmhub_v1_8_set_fault_enable_default(struct amdgpu_device *adev, bool value)
{
- u32 tmp;
+ u32 tmp, inst_mask;
int i;
if (amdgpu_sriov_vf(adev))
return;
- for (i = 0; i < adev->num_aid; i++) {
+ inst_mask = adev->aid_mask;
+ for_each_inst(i, inst_mask) {
tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL);
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
@@ -510,9 +524,11 @@ static void mmhub_v1_8_set_fault_enable_default(struct amdgpu_device *adev, bool
static void mmhub_v1_8_init(struct amdgpu_device *adev)
{
struct amdgpu_vmhub *hub;
+ u32 inst_mask;
int i;
- for (i = 0; i < adev->num_aid; i++) {
+ inst_mask = adev->aid_mask;
+ for_each_inst(i, inst_mask) {
hub = &adev->vmhub[AMDGPU_MMHUB0(i)];
hub->ctx0_ptb_addr_lo32 = SOC15_REG_OFFSET(MMHUB, i,
--
2.42.0