From c7ad3dc3649730af483ee1e78be5d0362da25bfe Mon Sep 17 00:00:00 2001
From: Jim Harris <jim.harris@samsung.com>
Date: Fri, 3 Nov 2023 20:18:34 +0000
Subject: [PATCH] cxl/region: fix x9 interleave typo
Git-commit: c7ad3dc3649730af483ee1e78be5d0362da25bfe
Patch-mainline: v6.8-rc1
References: git-fixes
CXL supports x3, x6 and x12 - not x9.
Fixes: 80d10a6cee050 ("cxl/region: Add interleave geometry attributes")
Signed-off-by: Jim Harris <jim.harris@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Link: https://lore.kernel.org/r/169904271254.204936.8580772404462743630.stgit@ubuntu
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/cxl/core/region.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index 3e817a6f94c6..76fec47a13a4 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -397,7 +397,7 @@ static ssize_t interleave_ways_store(struct device *dev,
return rc;
/*
- * Even for x3, x9, and x12 interleaves the region interleave must be a
+ * Even for x3, x6, and x12 interleaves the region interleave must be a
* power of 2 multiple of the host bridge interleave.
*/
if (!is_power_of_2(val / cxld->interleave_ways) ||
--
2.35.3