From: Michael Chan <michael.chan@broadcom.com>
Date: Mon, 11 Dec 2023 16:51:14 -0800
Subject: bnxt_en: Support TX coalesced completion on 5760X chips
Patch-mainline: v6.8-rc1
Git-commit: 6dea3ebe0d226e021970f3552ed37fdcedca8773
References: jsc#PED-7574
TX coalesced completions are supported on newer chips to provide
one TX completion record for multiple TX packets up to the
sq_cons_idx in the completion record. This method saves PCIe
bandwidth by reducing the number of TX completions.
Only very minor changes are now required to support this mode
with the new framework that handles TX completions based on
the consumer indices.
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
Link: https://lore.kernel.org/r/20231212005122.2401-6-michael.chan@broadcom.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
---
drivers/net/ethernet/broadcom/bnxt/bnxt.c | 13 +++++++++++--
drivers/net/ethernet/broadcom/bnxt/bnxt.h | 1 +
2 files changed, 12 insertions(+), 2 deletions(-)
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
@@ -2800,14 +2800,18 @@ static int __bnxt_poll_work(struct bnxt
*/
dma_rmb();
cmp_type = TX_CMP_TYPE(txcmp);
- if (cmp_type == CMP_TYPE_TX_L2_CMP) {
+ if (cmp_type == CMP_TYPE_TX_L2_CMP ||
+ cmp_type == CMP_TYPE_TX_L2_COAL_CMP) {
u32 opaque = txcmp->tx_cmp_opaque;
struct bnxt_tx_ring_info *txr;
u16 tx_freed;
txr = bnapi->tx_ring[TX_OPAQUE_RING(opaque)];
event |= BNXT_TX_CMP_EVENT;
- txr->tx_hw_cons = TX_OPAQUE_PROD(bp, opaque);
+ if (cmp_type == CMP_TYPE_TX_L2_COAL_CMP)
+ txr->tx_hw_cons = TX_CMP_SQ_CONS_IDX(txcmp);
+ else
+ txr->tx_hw_cons = TX_OPAQUE_PROD(bp, opaque);
tx_freed = (txr->tx_hw_cons - txr->tx_cons) &
bp->tx_ring_mask;
/* return full budget so NAPI will complete. */
@@ -6083,6 +6087,9 @@ static int hwrm_ring_alloc_send_msg(stru
req->length = cpu_to_le32(bp->tx_ring_mask + 1);
req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
req->queue_id = cpu_to_le16(ring->queue_id);
+ if (bp->flags & BNXT_FLAG_TX_COAL_CMPL)
+ req->cmpl_coal_cnt =
+ RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64;
break;
}
case HWRM_RING_ALLOC_RX:
@@ -8294,6 +8301,8 @@ static int __bnxt_hwrm_func_qcaps(struct
bp->fw_cap |= BNXT_FW_CAP_LIVEPATCH;
if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED)
bp->fw_cap |= BNXT_FW_CAP_BACKING_STORE_V2;
+ if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP)
+ bp->flags |= BNXT_FLAG_TX_COAL_CMPL;
flags_ext2 = le32_to_cpu(resp->flags_ext2);
if (flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED)
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.h
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.h
@@ -2053,6 +2053,7 @@ struct bnxt {
#define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
#define BNXT_FLAG_DIM 0x2000000
#define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
+ #define BNXT_FLAG_TX_COAL_CMPL 0x8000000
#define BNXT_FLAG_PORT_STATS_EXT 0x10000000
#define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \