From 06d71fa10f2e507444c6759328a6c19d38eab788 Mon Sep 17 00:00:00 2001
From: Imran Shaik <quic_imrashai@quicinc.com>
Date: Thu, 3 Aug 2023 16:27:37 +0530
Subject: [PATCH] clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock
Git-commit: 06d71fa10f2e507444c6759328a6c19d38eab788
Patch-mainline: v6.6-rc1
References: git-fixes
gcc_gpll1_out_even clock is referenced as a parent, but not registered
with the clock framework. Hence add support to register the same.
Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-5-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/clk/qcom/gcc-qdu1000.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 8df7b7983968..626c5afed780 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -2521,6 +2521,7 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = {
[GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr,
[GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr,
[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
+ [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr,
};
static const struct qcom_reset_map gcc_qdu1000_resets[] = {
--
2.35.3