From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Mon, 19 Jun 2023 20:34:01 +0530
Subject: PCI: qcom: Use DWC helpers for modifying the read-only DBI registers
Git-commit: 60f0072d7fb7996b9a524ef0d152e21205473192
Patch-mainline: 6.5-rc1
References: git-fixes
DWC core already exposes dw_pcie_dbi_ro_wr_{en/dis} helper APIs for
enabling and disabling the write access to read only DBI registers. So
let's use them instead of doing it manually.
Also, the existing code doesn't disable the write access when it's done.
This is also fixed now.
Link: https://lore.kernel.org/r/20230619150408.8468-3-manivannan.sadhasivam@linaro.org
Fixes: 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
---
drivers/pci/dwc/pcie-qcom.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -86,9 +86,6 @@
#define PCIE20_PARF_Q2A_FLUSH 0x1AC
-#define PCIE20_MISC_CONTROL_1_REG 0x8BC
-#define DBI_RO_WR_EN 1
-
#define PERST_DELAY_US 1000
/* PARF registers */
#define PCIE20_PARF_PCS_DEEMPH 0x34
@@ -1154,7 +1151,9 @@ static int qcom_pcie_init_2_3_3(struct q
writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS);
- writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
+
+ dw_pcie_dbi_ro_wr_en(pci);
+
writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1);
val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);