From: "Borislav Petkov (AMD)" <bp@alien8.de>
Date: Mon, 15 May 2023 16:07:26 +0200
Subject: x86/retbleed: Add __x86_return_thunk alignment checks
Git-commit: f220125b999b2c9694149c6bda2798d8096f47ed
Patch-mainline: v6.5-rc1
References: bsc#1213287, CVE-2023-20569
Add a linker assertion and compute the 0xcc padding dynamically so that
__x86_return_thunk is always cacheline-aligned. Leave the SYM_START()
macro in as the untraining doesn't need ENDBR annotations anyway.
Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Link: https://lore.kernel.org/r/20230515140726.28689-1-bp@alien8.de
Acked-by: Nikolay Borisov <nik.borisov@suse.com>
---
arch/x86/kernel/vmlinux.lds.S | 4 ++++
arch/x86/lib/retpoline.S | 5 +++--
2 files changed, 7 insertions(+), 2 deletions(-)
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -404,6 +404,10 @@ INIT_PER_CPU(irq_stack_union);
"irq_stack_union is not at start of per-cpu area");
#endif
+#ifdef CONFIG_RETPOLINE
+. = ASSERT((__x86_return_thunk & 0x3f) == 0, "__x86_return_thunk not cacheline-aligned");
+#endif
+
#endif /* CONFIG_X86_32 */
#ifdef CONFIG_KEXEC_CORE
--- a/arch/x86/lib/retpoline.S
+++ b/arch/x86/lib/retpoline.S
@@ -63,7 +63,7 @@ GENERATE_THUNK(r15)
* from re-poisioning the BTB prediction.
*/
.align 64
- .skip 63, 0xcc
+ .skip 64 - (__x86_return_thunk - zen_untrain_ret), 0xcc
.globl zen_untrain_ret;
zen_untrain_ret:
@@ -97,7 +97,8 @@ zen_untrain_ret:
* which will be contained safely by the INT3.
*/
-ENTRY(__x86_return_thunk)
+.globl __x86_return_thunk;
+__x86_return_thunk:
ret
int3
ENDPROC(__x86_return_thunk)