From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Date: Thu, 29 Jun 2017 17:34:55 +0200
Subject: PCI: qcom: Limit TLP size to 2K to work around hardware issue

Git-commit: b8f2a856560361753a6ac846977e4c1e21bf64f7
Patch-mainline: v4.13-rc1
References: fate#326536, fate#326532

Limit TLP size to 2K to work around a hardware bug in the v0 version of
PCIe IP.  When using default TLP size of 4K, the internal buffer gets
corrupted due to this hardware bug.

This bug was originally noticed during ssh session between APQ8064-based
board and PC.  Network packets got corrupted randomly and terminated the ssh
session due to this bug.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
---
 drivers/pci/dwc/pcie-qcom.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index fbc79a5274c6..2a4a66754878 100644
--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -51,6 +51,12 @@
 #define PCIE20_ELBI_SYS_CTRL			0x04
 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE		BIT(0)
 
+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0		0x818
+#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K	0x4
+#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K	0x5
+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1		0x81c
+#define CFG_BRIDGE_SB_INIT			BIT(0)
+
 #define PCIE20_CAP				0x70
 
 #define PERST_DELAY_US				1000
@@ -336,6 +342,13 @@ static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
 	/* wait for clock acquisition */
 	usleep_range(1000, 1500);
 
+
+	/* Set the Max TLP size to 2K, instead of using default of 4K */
+	writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
+	       pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
+	writel(CFG_BRIDGE_SB_INIT,
+	       pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
+
 	return 0;
 
 err_deassert_ahb:
-- 
2.11.0