From 71ffd49cc9b9da5d9e97b5153ee1fe33dfd61a43 Mon Sep 17 00:00:00 2001
From: Anuj Phogat <anuj.phogat@gmail.com>
Date: Thu, 4 Oct 2018 11:29:39 -0700
Subject: drm/i915/icl:Add Wa_1606682166
Git-commit: 71ffd49cc9b9da5d9e97b5153ee1fe33dfd61a43
Patch-mainline: v5.0-rc1
References: fate#326289
Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
Disable the Sampler state prefetch functionality in the SARB by
programming 0xB000[30] to '1'. This is to be done at boot time
and the feature must remain disabled permanently.
Fixes flaky tex-mip-level-selection* piglit tests with Mesa i965
driver.
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181004182939.7668-6-radhakrishna.sripada@intel.com
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7420,6 +7420,7 @@ enum {
#define GEN7_SARCHKMD _MMIO(0xB000)
#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
+#define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
#define GEN7_L3SQCREG1 _MMIO(0xB010)
#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -900,7 +900,8 @@ static void icl_gt_workarounds_init(stru
if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
I915_WRITE(GEN7_SARCHKMD,
I915_READ(GEN7_SARCHKMD) |
- GEN7_DISABLE_DEMAND_PREFETCH);
+ GEN7_DISABLE_DEMAND_PREFETCH |
+ GEN7_DISABLE_SAMPLER_PREFETCH);
}
void intel_gt_init_workarounds(struct drm_i915_private *i915)