From: Hawking Zhang <Hawking.Zhang@amd.com>
Date: Fri, 10 Feb 2017 15:47:28 +0800
Subject: drm/amdgpu/gfx9: add enable/disable funcs for cp power gating
Git-commit: 3a6cc4776d06411e02c1a0b3ab8f6efc27ddef82
Patch-mainline: v4.13-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

Used to enable/disable cp powergating.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |   25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1941,6 +1941,25 @@ static void gfx_v9_0_enable_sck_slow_dow
 	}
 }
 
+static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
+					bool enable)
+{
+	uint32_t data = 0;
+	uint32_t default_data = 0;
+
+	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
+
+	if (enable == true) {
+		data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
+		if(default_data != data)
+			WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+	} else {
+		data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
+		if(default_data != data)
+			WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+	}
+}
+
 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
 {
 	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
@@ -1957,6 +1976,7 @@ static void gfx_v9_0_init_pg(struct amdg
 			WREG32(mmRLC_JUMP_TABLE_RESTORE,
 				adev->gfx.rlc.cp_table_gpu_addr >> 8);
 			gfx_v9_0_init_gfx_power_gating(adev);
+
 			if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
 				gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
 				gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
@@ -1964,6 +1984,11 @@ static void gfx_v9_0_init_pg(struct amdg
 				gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
 				gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
 			}
+
+			if (adev->pg_flags & AMD_PG_SUPPORT_CP)
+				gfx_v9_0_enable_cp_power_gating(adev, true);
+			else
+				gfx_v9_0_enable_cp_power_gating(adev, false);
 		}
 	}
 }