From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Date: Thu, 3 Aug 2017 10:19:58 -0400
Subject: drm/amd/display: Use function pointer for update_plane_addr
Git-commit: 503a7c6f2518be909fa61276ee002846524b588b
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c         |    2 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c     |    1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c |    6 +++---
 3 files changed, 5 insertions(+), 4 deletions(-)

--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -132,7 +132,7 @@ struct resource_pool *dc_create_resource
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 	case DCN_VERSION_1_0:
 		res_pool = dcn10_create_resource_pool(
-			num_virtual_links, dc);
+				num_virtual_links, dc);
 		break;
 #endif
 
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -615,6 +615,7 @@ static uint32_t dce110_get_pll_pixel_rat
 
 	/* This function need separate to different DCE version, before separate, just use pixel clock */
 	return pipe_ctx->stream->phy_pix_clk;
+
 }
 
 static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll(
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1246,7 +1246,7 @@ static void toggle_watermark_change_req(
 			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);
 }
 
-static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx)
+static void dcn10_update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx)
 {
 	bool addr_patched = false;
 	PHYSICAL_ADDRESS_LOC addr;
@@ -2115,7 +2115,7 @@ static void update_dchubp_dpp(
 	 */
 	REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst);
 
-	update_plane_addr(dc, pipe_ctx);
+	dc->hwss.update_plane_addr(dc, pipe_ctx);
 
 	mi->funcs->mem_input_setup(
 		mi,
@@ -2687,7 +2687,7 @@ static const struct hw_sequencer_funcs d
 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
 	.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
 	.set_plane_config = set_plane_config,
-	.update_plane_addr = update_plane_addr,
+	.update_plane_addr = dcn10_update_plane_addr,
 	.update_dchub = dcn10_update_dchub,
 	.update_pending_status = dcn10_update_pending_status,
 	.set_input_transfer_func = dcn10_set_input_transfer_func,