From: Eric Bernstein <eric.bernstein@amd.com>
Date: Thu, 31 Aug 2017 16:04:24 -0400
Subject: drm/amd/display: remove output_format from ipp_setup
Git-commit: 264efa31835dd87af4e77e3a27090e60d4fe1511
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c          |    3 +--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h          |    3 +--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c       |    4 ++--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c |    3 +--
 drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h               |    3 +--
 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h         |    3 +--
 6 files changed, 7 insertions(+), 12 deletions(-)

--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -266,8 +266,7 @@ static void ippn10_set_degamma_format_fl
 void ippn10_cnv_setup (
 		struct transform *xfm_base,
 		enum surface_pixel_format input_format,
-		enum expansion_mode mode,
-		enum ipp_output_format cnv_out_format)
+		enum expansion_mode mode)
 {
 	uint32_t pixel_format;
 	uint32_t alpha_en;
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -1358,8 +1358,7 @@ void dcn10_dpp_dscl_set_scaler_manual_sc
 void ippn10_cnv_setup (
 		struct transform *xfm_base,
 		enum surface_pixel_format input_format,
-		enum expansion_mode mode,
-		enum ipp_output_format cnv_out_format);
+		enum expansion_mode mode);
 
 void ippn10_full_bypass(struct transform *xfm_base);
 
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -727,11 +727,11 @@ void ippn10_full_bypass(struct transform
 			FORMAT_EXPANSION_MODE, 0);
 
 	/* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */
-	REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
+	if (xfm->tf_mask->CM_BYPASS_EN)
+		REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
 
 	/* Setting degamma bypass for now */
 	REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);
-	REG_SET(CM_IGAM_CONTROL, 0, CM_IGAM_LUT_MODE, 0);
 }
 
 static bool ippn10_ingamma_ram_inuse(struct transform *xfm_base,
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2316,8 +2316,7 @@ static void update_dchubp_dpp(
 
 	xfm->funcs->ipp_setup(xfm,
 			plane_state->format,
-			1,
-			IPP_OUTPUT_FORMAT_12_BIT_FIX);
+			EXPANSION_MODE_ZERO);
 
 	mpcc_cfg.mi = mi;
 	mpcc_cfg.opp = pipe_ctx->stream_res.opp;
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
@@ -86,8 +86,7 @@ struct ipp_funcs {
 	void (*ipp_setup)(
 		struct input_pixel_processor *ipp,
 		enum surface_pixel_format input_format,
-		enum expansion_mode mode,
-		enum ipp_output_format output_format);
+		enum expansion_mode mode);
 
 	/* DCE function to setup IPP.  TODO: see if we can consolidate to setup */
 	void (*ipp_program_prescale)(
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
@@ -234,8 +234,7 @@ struct transform_funcs {
 	void (*ipp_setup)(
 			struct transform *xfm_base,
 			enum surface_pixel_format input_format,
-			enum expansion_mode mode,
-			enum ipp_output_format cnv_out_format);
+			enum expansion_mode mode);
 
 	void (*ipp_full_bypass)(struct transform *xfm_base);