From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Date: Fri, 16 Feb 2018 13:57:42 -0500
Subject: drm/amd/display: Use MACROS instead of dm_logger
Git-commit: 2f3fd67a8af25f5b4d549c3e9cc515dbf1839ffc
Patch-mainline: v4.17-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
Created MACROS for all log levels. Also Replaced
usage of dm_logger_write to the defined MACROS
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 2
drivers/gpu/drm/amd/display/dc/bios/command_table2.c | 6 -
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 6 -
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 -
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 32 +++----
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 34 +++----
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 2
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 10 +-
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 24 ++---
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 4
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 10 +-
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 6 -
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 6 -
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c | 12 +-
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 16 +--
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 6 -
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c | 10 +-
drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c | 2
drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c | 32 +++----
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 6 -
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 44 +++++-----
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 28 +++---
drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c | 4
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c | 4
drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c | 8 -
drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 8 -
drivers/gpu/drm/amd/display/include/logger_types.h | 33 +++++++
28 files changed, 199 insertions(+), 166 deletions(-)
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -3079,7 +3079,7 @@ static enum bp_result patch_bios_image_f
opm_object,
&ext_display_connection_info_tbl) != BP_RESULT_OK) {
- dm_logger_write(bp->base.ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(bp->base.ctx->logger,
"%s: Failed to read Connection Info Table", __func__);
return BP_RESULT_UNSUPPORTED;
}
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
@@ -239,7 +239,7 @@ static enum bp_result transmitter_contro
if (cntl->action == TRANSMITTER_CONTROL_ENABLE ||
cntl->action == TRANSMITTER_CONTROL_ACTIAVATE ||
cntl->action == TRANSMITTER_CONTROL_DEACTIVATE) {
- dm_logger_write(bp->base.ctx->logger, LOG_BIOS,\
+ DC_LOG_BIOS(bp->base.ctx->logger, \
"%s:ps.param.symclk_10khz = %d\n",\
__func__, ps.param.symclk_10khz);
}
@@ -331,7 +331,7 @@ static enum bp_result set_pixel_clock_v7
(uint8_t) bp->cmd_helper->
transmitter_color_depth_to_atom(
bp_params->color_depth);
- dm_logger_write(bp->base.ctx->logger, LOG_BIOS,\
+ DC_LOG_BIOS(bp->base.ctx->logger, \
"%s:program display clock = %d"\
"colorDepth = %d\n", __func__,\
bp_params->target_pixel_clock, bp_params->color_depth);
@@ -772,7 +772,7 @@ static enum bp_result set_dce_clock_v2_1
*/
params.param.dceclk_10khz = cpu_to_le32(
bp_params->target_clock_frequency / 10);
- dm_logger_write(bp->base.ctx->logger, LOG_BIOS,
+ DC_LOG_BIOS(bp->base.ctx->logger,
"%s:target_clock_frequency = %d"\
"clock_type = %d \n", __func__,\
bp_params->target_clock_frequency,\
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1242,7 +1242,7 @@ unsigned int dcn_find_dcfclk_suits_all(
else
dcf_clk = dc->dcn_soc->dcfclkv_min0p65*1000;
- dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
"\tdcf_clk for voltage = %d\n", dcf_clk);
return dcf_clk;
}
@@ -1441,7 +1441,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(st
void dcn_bw_sync_calcs_and_dml(struct dc *dc)
{
kernel_fpu_begin();
- dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
"sr_exit_time: %d ns\n"
"sr_enter_plus_exit_time: %d ns\n"
"urgent_latency: %d ns\n"
@@ -1510,7 +1510,7 @@ void dcn_bw_sync_calcs_and_dml(struct dc
dc->dcn_soc->vmm_page_size,
dc->dcn_soc->dram_clock_change_latency * 1000,
dc->dcn_soc->return_bus_width);
- dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
"rob_buffer_size_in_kbyte: %d\n"
"det_buffer_size_in_kbyte: %d\n"
"dpp_output_buffer_pixels: %d\n"
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -264,7 +264,7 @@ bool dc_stream_configure_crc(struct dc *
/* Only call if supported */
if (tg->funcs->configure_crc)
return tg->funcs->configure_crc(tg, ¶m);
- dm_logger_write(dc->ctx->logger, LOG_WARNING, "CRC capture not supported.");
+ DC_LOG_WARNING(dc->ctx->logger, "CRC capture not supported.");
return false;
}
@@ -297,7 +297,7 @@ bool dc_stream_get_crc(struct dc *dc, st
if (tg->funcs->get_crc)
return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
- dm_logger_write(dc->ctx->logger, LOG_WARNING, "CRC capture not supported.");
+ DC_LOG_WARNING(dc->ctx->logger, "CRC capture not supported.");
return false;
}
@@ -618,7 +618,7 @@ struct dc *dc_create(const struct dc_ini
dc->config = init_params->flags;
- dm_logger_write(dc->ctx->logger, LOG_DC,
+ DC_LOG_DC(dc->ctx->logger,
"Display Core initialized\n");
@@ -888,7 +888,7 @@ bool dc_commit_state(struct dc *dc, stru
if (false == context_changed(dc, context))
return DC_OK;
- dm_logger_write(dc->ctx->logger, LOG_DC, "%s: %d streams\n",
+ DC_LOG_DC(dc->ctx->logger, "%s: %d streams\n",
__func__, context->stream_count);
for (i = 0; i < context->stream_count; i++) {
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -47,7 +47,7 @@
#include "dce/dce_11_0_sh_mask.h"
#define LINK_INFO(...) \
- dm_logger_write(dc_ctx->logger, LOG_HW_HOTPLUG, \
+ DC_LOG_HW_HOTPLUG(dc_ctx->logger, \
__VA_ARGS__)
/*******************************************************************************
@@ -677,11 +677,11 @@ bool dc_link_detect(struct dc_link *link
switch (edid_status) {
case EDID_BAD_CHECKSUM:
- dm_logger_write(link->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(link->ctx->logger,
"EDID checksum invalid.\n");
break;
case EDID_NO_RESPONSE:
- dm_logger_write(link->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(link->ctx->logger,
"No EDID read.\n");
default:
break;
@@ -712,7 +712,7 @@ bool dc_link_detect(struct dc_link *link
"%s: [Block %d] ", sink->edid_caps.display_name, i);
}
- dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER,
+ DC_LOG_DETECTION_EDID_PARSER(link->ctx->logger,
"%s: "
"manufacturer_id = %X, "
"product_id = %X, "
@@ -733,7 +733,7 @@ bool dc_link_detect(struct dc_link *link
sink->edid_caps.audio_mode_count);
for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
- dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER,
+ DC_LOG_DETECTION_EDID_PARSER(link->ctx->logger,
"%s: mode number = %d, "
"format_code = %d, "
"channel_count = %d, "
@@ -984,7 +984,7 @@ static bool construct(
}
break;
default:
- dm_logger_write(dc_ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(dc_ctx->logger,
"Unsupported Connector type:%d!\n", link->link_id.id);
goto create_fail;
}
@@ -1175,7 +1175,7 @@ static void dpcd_configure_panel_mode(
ASSERT(result == DDC_RESULT_SUCESSFULL);
}
}
- dm_logger_write(link->ctx->logger, LOG_DETECTION_DP_CAPS,
+ DC_LOG_DETECTION_DP_CAPS(link->ctx->logger,
"Link: %d eDP panel mode supported: %d "
"eDP panel mode enabled: %d \n",
link->link_index,
@@ -1965,7 +1965,7 @@ bool dc_link_set_backlight_level(const s
use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
- dm_logger_write(link->ctx->logger, LOG_BACKLIGHT,
+ DC_LOG_BACKLIGHT(link->ctx->logger,
"New Backlight level: %d (0x%X)\n", level, level);
if (dc_is_embedded_signal(link->connector_signal)) {
@@ -2150,20 +2150,20 @@ static enum dc_status allocate_mst_paylo
link, pipe_ctx->stream_res.stream_enc, &proposed_table);
}
else
- dm_logger_write(link->ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(link->ctx->logger,
"Failed to update"
"MST allocation table for"
"pipe idx:%d\n",
pipe_ctx->pipe_idx);
- dm_logger_write(link->ctx->logger, LOG_MST,
+ DC_LOG_MST(link->ctx->logger,
"%s "
"stream_count: %d: \n ",
__func__,
link->mst_stream_alloc_table.stream_count);
for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
- dm_logger_write(link->ctx->logger, LOG_MST,
+ DC_LOG_MST(link->ctx->logger,
"stream_enc[%d]: 0x%x "
"stream[%d].vcp_id: %d "
"stream[%d].slot_count: %d\n",
@@ -2240,7 +2240,7 @@ static enum dc_status deallocate_mst_pay
link, pipe_ctx->stream_res.stream_enc, &proposed_table);
}
else {
- dm_logger_write(link->ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(link->ctx->logger,
"Failed to update"
"MST allocation table for"
"pipe idx:%d\n",
@@ -2248,14 +2248,14 @@ static enum dc_status deallocate_mst_pay
}
}
- dm_logger_write(link->ctx->logger, LOG_MST,
+ DC_LOG_MST(link->ctx->logger,
"%s"
"stream_count: %d: ",
__func__,
link->mst_stream_alloc_table.stream_count);
for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
- dm_logger_write(link->ctx->logger, LOG_MST,
+ DC_LOG_MST(link->ctx->logger,
"stream_enc[%d]: 0x%x "
"stream[%d].vcp_id: %d "
"stream[%d].slot_count: %d\n",
@@ -2307,8 +2307,8 @@ void core_link_enable_stream(
status = enable_link(state, pipe_ctx);
if (status != DC_OK) {
- dm_logger_write(pipe_ctx->stream->ctx->logger,
- LOG_WARNING, "enabling link %u failed: %d\n",
+ DC_LOG_WARNING(pipe_ctx->stream->ctx->logger,
+ "enabling link %u failed: %d\n",
pipe_ctx->stream->sink->link->link_index,
status);
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -63,7 +63,7 @@ static void wait_for_training_aux_rd_int
udelay(default_wait_in_micro_secs);
- dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
+ DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
"%s:\n wait = %d\n",
__func__,
default_wait_in_micro_secs);
@@ -79,7 +79,7 @@ static void dpcd_set_training_pattern(
&dpcd_pattern.raw,
1);
- dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
+ DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
"%s\n %x pattern = %x\n",
__func__,
DP_TRAINING_PATTERN_SET,
@@ -116,7 +116,7 @@ static void dpcd_set_link_settings(
core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
&downspread.raw, sizeof(downspread));
- dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
+ DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
"%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
__func__,
DP_LINK_BW_SET,
@@ -151,7 +151,7 @@ static enum dpcd_training_patterns
break;
default:
ASSERT(0);
- dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
+ DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
"%s: Invalid HW Training pattern: %d\n",
__func__, pattern);
break;
@@ -184,7 +184,7 @@ static void dpcd_set_lt_pattern_and_lane
dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
= dpcd_pattern.raw;
- dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
+ DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
"%s\n %x pattern = %x\n",
__func__,
DP_TRAINING_PATTERN_SET,
@@ -219,7 +219,7 @@ static void dpcd_set_lt_pattern_and_lane
dpcd_lane,
size_in_bytes);
- dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
+ DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
"%s:\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
__func__,
DP_TRAINING_LANE0_SET,
@@ -456,13 +456,13 @@ static void get_lane_status_and_drive_se
ln_status_updated->raw = dpcd_buf[2];
- dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
+ DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
"%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
__func__,
DP_LANE0_1_STATUS, dpcd_buf[0],
DP_LANE2_3_STATUS, dpcd_buf[1]);
- dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
+ DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
"%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
__func__,
DP_ADJUST_REQUEST_LANE0_1,
@@ -556,7 +556,7 @@ static void dpcd_set_lane_settings(
}
*/
- dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
+ DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
"%s\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
__func__,
DP_TRAINING_LANE0_SET,
@@ -669,7 +669,7 @@ static bool perform_post_lt_adj_req_sequ
}
if (!req_drv_setting_changed) {
- dm_logger_write(link->ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(link->ctx->logger,
"%s: Post Link Training Adjust Request Timed out\n",
__func__);
@@ -677,7 +677,7 @@ static bool perform_post_lt_adj_req_sequ
return true;
}
}
- dm_logger_write(link->ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(link->ctx->logger,
"%s: Post Link Training Adjust Request limit reached\n",
__func__);
@@ -885,7 +885,7 @@ static enum link_training_result perform
if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
ASSERT(0);
- dm_logger_write(link->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(link->ctx->logger,
"%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
__func__,
LINK_TRAINING_MAX_CR_RETRY);
@@ -1606,7 +1606,7 @@ static bool hpd_rx_irq_check_link_loss_s
if (sink_status_changed ||
!hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
- dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
+ DC_LOG_HW_HPD_IRQ(link->ctx->logger,
"%s: Link Status changed.\n", __func__);
return_code = true;
@@ -1620,7 +1620,7 @@ static bool hpd_rx_irq_check_link_loss_s
sizeof(irq_reg_rx_power_state));
if (dpcd_result != DC_OK) {
- dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
+ DC_LOG_HW_HPD_IRQ(link->ctx->logger,
"%s: DPCD read failed to obtain power state.\n",
__func__);
} else {
@@ -1982,7 +1982,7 @@ bool dc_link_handle_hpd_rx_irq(struct dc
* PSR and device auto test, refer to function handle_sst_hpd_irq
* in DAL2.1*/
- dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
+ DC_LOG_HW_HPD_IRQ(link->ctx->logger,
"%s: Got short pulse HPD on link %d\n",
__func__, link->link_index);
@@ -1997,7 +1997,7 @@ bool dc_link_handle_hpd_rx_irq(struct dc
*out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
if (result != DC_OK) {
- dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
+ DC_LOG_HW_HPD_IRQ(link->ctx->logger,
"%s: DPCD read failed to obtain irq data\n",
__func__);
return false;
@@ -2016,7 +2016,7 @@ bool dc_link_handle_hpd_rx_irq(struct dc
}
if (!allow_hpd_rx_irq(link)) {
- dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
+ DC_LOG_HW_HPD_IRQ(link->ctx->logger,
"%s: skipping HPD handling on %d\n",
__func__, link->link_index);
return false;
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -893,7 +893,7 @@ bool resource_build_scaling_params(struc
/* May need to re-check lb size after this in some obscure scenario */
calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
- dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER,
+ DC_LOG_SCALER(pipe_ctx->stream->ctx->logger,
"%s: Viewport:\nheight:%d width:%d x:%d "
"y:%d\n dst_rect:\nheight:%d width:%d x:%d "
"y:%d\n",
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -403,7 +403,7 @@ static bool dce_abm_set_backlight_level(
{
struct dce_abm *abm_dce = TO_DCE_ABM(abm);
- dm_logger_write(abm->ctx->logger, LOG_BACKLIGHT,
+ DC_LOG_BACKLIGHT(abm->ctx->logger,
"New Backlight level: %d (0x%X)\n",
backlight_level, backlight_level);
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -63,7 +63,7 @@ static void write_indirect_azalia_reg(st
REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,
AZALIA_ENDPOINT_REG_DATA, reg_data);
- dm_logger_write(CTX->logger, LOG_HW_AUDIO,
+ DC_LOG_HW_AUDIO(CTX->logger,
"AUDIO:write_indirect_azalia_reg: index: %u data: %u\n",
reg_index, reg_data);
}
@@ -81,7 +81,7 @@ static uint32_t read_indirect_azalia_reg
/* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
- dm_logger_write(CTX->logger, LOG_HW_AUDIO,
+ DC_LOG_HW_AUDIO(CTX->logger,
"AUDIO:read_indirect_azalia_reg: index: %u data: %u\n",
reg_index, value);
@@ -364,7 +364,7 @@ void dce_aud_az_enable(struct audio *aud
CLOCK_GATING_DISABLE);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
- dm_logger_write(CTX->logger, LOG_HW_AUDIO,
+ DC_LOG_HW_AUDIO(CTX->logger,
"\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n",
audio->inst, value);
}
@@ -390,7 +390,7 @@ void dce_aud_az_disable(struct audio *au
CLOCK_GATING_DISABLE);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
- dm_logger_write(CTX->logger, LOG_HW_AUDIO,
+ DC_LOG_HW_AUDIO(CTX->logger,
"\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n",
audio->inst, value);
}
@@ -795,7 +795,7 @@ void dce_aud_wall_dto_setup(
crtc_info->calculated_pixel_clock,
&clock_info);
- dm_logger_write(audio->ctx->logger, LOG_HW_AUDIO,\
+ DC_LOG_HW_AUDIO(audio->ctx->logger, \
"\n%s:Input::requested_pixel_clock = %d"\
"calculated_pixel_clock =%d\n"\
"audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -288,7 +288,7 @@ static uint32_t calculate_pixel_clock_pl
uint32_t max_ref_divider;
if (pll_settings->adjusted_pix_clk == 0) {
- dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(calc_pll_cs->ctx->logger,
"%s Bad requested pixel clock", __func__);
return MAX_PLL_CALC_ERROR;
}
@@ -349,13 +349,13 @@ static uint32_t calculate_pixel_clock_pl
* ## SVS Wed 15 Jul 2009 */
if (min_post_divider > max_post_divider) {
- dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(calc_pll_cs->ctx->logger,
"%s Post divider range is invalid", __func__);
return MAX_PLL_CALC_ERROR;
}
if (min_ref_divider > max_ref_divider) {
- dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(calc_pll_cs->ctx->logger,
"%s Reference divider range is invalid", __func__);
return MAX_PLL_CALC_ERROR;
}
@@ -493,7 +493,7 @@ static uint32_t dce110_get_pix_clk_divid
if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
/* Should never happen, ASSERT and fill up values to be able
* to continue. */
- dm_logger_write(clk_src->base.ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(clk_src->base.ctx->logger,
"%s: Failed to adjust pixel clock!!", __func__);
pll_settings->actual_pix_clk =
pix_clk_params->requested_pix_clk;
@@ -560,7 +560,7 @@ static uint32_t dce110_get_pix_clk_divid
if (pix_clk_params == NULL || pll_settings == NULL
|| pix_clk_params->requested_pix_clk == 0) {
- dm_logger_write(clk_src->base.ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(clk_src->base.ctx->logger,
"%s: Invalid parameters!!\n", __func__);
return pll_calc_error;
}
@@ -1054,12 +1054,12 @@ static void get_ss_info_from_atombios(
uint32_t i;
if (ss_entries_num == NULL) {
- dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
+ DC_LOG_SYNC(clk_src->base.ctx->logger,
"Invalid entry !!!\n");
return;
}
if (spread_spectrum_data == NULL) {
- dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
+ DC_LOG_SYNC(clk_src->base.ctx->logger,
"Invalid array pointer!!!\n");
return;
}
@@ -1104,7 +1104,7 @@ static void get_ss_info_from_atombios(
++i, ++ss_info_cur, ++ss_data_cur) {
if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
- dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
+ DC_LOG_SYNC(clk_src->base.ctx->logger,
"Invalid ATOMBIOS SS Table!!!\n");
goto out_free_data;
}
@@ -1114,9 +1114,9 @@ static void get_ss_info_from_atombios(
if (as_signal == AS_SIGNAL_TYPE_HDMI
&& ss_info_cur->spread_spectrum_percentage > 6){
/* invalid input, do nothing */
- dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
+ DC_LOG_SYNC(clk_src->base.ctx->logger,
"Invalid SS percentage ");
- dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
+ DC_LOG_SYNC(clk_src->base.ctx->logger,
"for HDMI in ATOMBIOS info Table!!!\n");
continue;
}
@@ -1228,12 +1228,12 @@ static bool calc_pll_max_vco_construct(
if (init_data->num_fract_fb_divider_decimal_point == 0 ||
init_data->num_fract_fb_divider_decimal_point_precision >
init_data->num_fract_fb_divider_decimal_point) {
- dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(calc_pll_cs->ctx->logger,
"The dec point num or precision is incorrect!");
return false;
}
if (init_data->num_fract_fb_divider_decimal_point_precision == 0) {
- dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(calc_pll_cs->ctx->logger,
"Incorrect fract feedback divider precision num!");
return false;
}
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -292,7 +292,7 @@ static enum dm_pp_clocks_state dce_get_r
low_req_clk = i + 1;
if (low_req_clk > clk->max_clks_state) {
- dm_logger_write(clk->ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(clk->ctx->logger,
"%s: clocks unsupported disp_clk %d pix_clk %d",
__func__,
req_clocks->display_clk_khz,
@@ -312,7 +312,7 @@ static bool dce_clock_set_min_clocks_sta
if (clocks_state > clk->max_clks_state) {
/*Requested state exceeds max supported state.*/
- dm_logger_write(clk->ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(clk->ctx->logger,
"Requested state exceeds max supported state");
return false;
} else if (clocks_state == clk->cur_min_clks_state) {
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -837,7 +837,7 @@ void dce110_link_encoder_hw_init(
result = link_transmitter_control(enc110, &cntl);
if (result != BP_RESULT_OK) {
- dm_logger_write(ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(ctx->logger,
"%s: Failed to execute VBIOS command table!\n",
__func__);
BREAK_TO_DEBUGGER();
@@ -938,7 +938,7 @@ void dce110_link_encoder_enable_tmds_out
result = link_transmitter_control(enc110, &cntl);
if (result != BP_RESULT_OK) {
- dm_logger_write(ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(ctx->logger,
"%s: Failed to execute VBIOS command table!\n",
__func__);
BREAK_TO_DEBUGGER();
@@ -979,7 +979,7 @@ void dce110_link_encoder_enable_dp_outpu
result = link_transmitter_control(enc110, &cntl);
if (result != BP_RESULT_OK) {
- dm_logger_write(ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(ctx->logger,
"%s: Failed to execute VBIOS command table!\n",
__func__);
BREAK_TO_DEBUGGER();
@@ -1020,7 +1020,7 @@ void dce110_link_encoder_enable_dp_mst_o
result = link_transmitter_control(enc110, &cntl);
if (result != BP_RESULT_OK) {
- dm_logger_write(ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(ctx->logger,
"%s: Failed to execute VBIOS command table!\n",
__func__);
BREAK_TO_DEBUGGER();
@@ -1063,7 +1063,7 @@ void dce110_link_encoder_disable_output(
result = link_transmitter_control(enc110, &cntl);
if (result != BP_RESULT_OK) {
- dm_logger_write(ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(ctx->logger,
"%s: Failed to execute VBIOS command table!\n",
__func__);
BREAK_TO_DEBUGGER();
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -277,8 +277,8 @@ static void dce110_update_hdmi_info_pack
#endif
default:
/* invalid HW packet index */
- dm_logger_write(
- ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(
+ ctx->logger,
"Invalid HW packet index: %s()\n",
__func__);
return;
@@ -1386,7 +1386,7 @@ static void dce110_se_setup_hdmi_audio(
crtc_info->requested_pixel_clock,
crtc_info->calculated_pixel_clock,
&audio_clock_info);
- dm_logger_write(enc->ctx->logger, LOG_HW_AUDIO,
+ DC_LOG_HW_AUDIO(enc->ctx->logger,
"\n%s:Input::requested_pixel_clock = %d" \
"calculated_pixel_clock = %d \n", __func__, \
crtc_info->requested_pixel_clock, \
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -693,7 +693,7 @@ static int dce_transform_get_max_num_of_
break;
default:
- dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(xfm_dce->base.ctx->logger,
"%s: Invalid LB pixel depth",
__func__);
BREAK_TO_DEBUGGER();
@@ -791,7 +791,7 @@ static void dce_transform_set_pixel_stor
if (!(xfm_dce->lb_pixel_depth_supported & depth)) {
/*we should use unsupported capabilities
* unless it is required by w/a*/
- dm_logger_write(xfm->ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(xfm->ctx->logger,
"%s: Capability not supported",
__func__);
}
@@ -1172,7 +1172,7 @@ static void program_pwl(struct dce_trans
}
if (counter == max_tries) {
- dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(xfm_dce->base.ctx->logger,
"%s: regamma lut was not powered on "
"in a timely manner,"
" programming still proceeds\n",
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -120,13 +120,13 @@ static void wait_for_fbc_state_changed(
}
if (counter == 10) {
- dm_logger_write(
- cp110->base.ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(
+ cp110->base.ctx->logger,
"%s: wait counter exceeded, changes to HW not applied",
__func__);
} else {
- dm_logger_write(
- cp110->base.ctx->logger, LOG_SYNC,
+ DC_LOG_SYNC(
+ cp110->base.ctx->logger,
"FBC status changed to %d", enabled);
}
@@ -310,8 +310,8 @@ void dce110_compressor_program_compresse
if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
fbc_pitch = fbc_pitch / 8;
else
- dm_logger_write(
- compressor->ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(
+ compressor->ctx->logger,
"%s: Unexpected DCE11 compression ratio",
__func__);
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -819,7 +819,7 @@ void hwss_edp_wait_for_hpd_ready(
dal_gpio_destroy_irq(&hpd);
if (false == edp_hpd_high) {
- dm_logger_write(ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(ctx->logger,
"%s: wait timed out!\n", __func__);
}
}
@@ -843,7 +843,7 @@ void hwss_edp_power_control(
if (power_up != is_panel_powered_on(hwseq)) {
/* Send VBIOS command to prompt eDP panel power */
- dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
+ DC_LOG_HW_RESUME_S3(ctx->logger,
"%s: Panel Power action: %s\n",
__func__, (power_up ? "On":"Off"));
@@ -859,11 +859,11 @@ void hwss_edp_power_control(
bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
if (bp_result != BP_RESULT_OK)
- dm_logger_write(ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(ctx->logger,
"%s: Panel Power bp_result: %d\n",
__func__, bp_result);
} else {
- dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
+ DC_LOG_HW_RESUME_S3(ctx->logger,
"%s: Skipping Panel Power action: %s\n",
__func__, (power_up ? "On":"Off"));
}
@@ -889,7 +889,7 @@ void hwss_edp_backlight_control(
}
if (enable && is_panel_backlight_on(hws)) {
- dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
+ DC_LOG_HW_RESUME_S3(ctx->logger,
"%s: panel already powered up. Do nothing.\n",
__func__);
return;
@@ -897,7 +897,7 @@ void hwss_edp_backlight_control(
/* Send VBIOS command to control eDP panel backlight */
- dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
+ DC_LOG_HW_RESUME_S3(ctx->logger,
"%s: backlight action: %s\n",
__func__, (enable ? "On":"Off"));
@@ -2765,7 +2765,7 @@ static void dce110_program_front_end_for
if (pipe_ctx->plane_state->update_flags.bits.full_update)
dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
- dm_logger_write(dc->ctx->logger, LOG_SURFACE,
+ DC_LOG_SURFACE(dc->ctx->logger,
"Pipe:%d 0x%x: addr hi:0x%x, "
"addr low:0x%x, "
"src: %d, %d, %d,"
@@ -2788,7 +2788,7 @@ static void dce110_program_front_end_for
pipe_ctx->plane_state->clip_rect.width,
pipe_ctx->plane_state->clip_rect.height);
- dm_logger_write(dc->ctx->logger, LOG_SURFACE,
+ DC_LOG_SURFACE(dc->ctx->logger,
"Pipe %d: width, height, x, y\n"
"viewport:%d, %d, %d, %d\n"
"recout: %d, %d, %d, %d\n",
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -771,8 +771,8 @@ static bool dce110_validate_bandwidth(
{
bool result = false;
- dm_logger_write(
- dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(
+ dc->ctx->logger,
"%s: start",
__func__);
@@ -786,7 +786,7 @@ static bool dce110_validate_bandwidth(
result = true;
if (!result)
- dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
+ DC_LOG_BANDWIDTH_VALIDATION(dc->ctx->logger,
"%s: %dx%d@%d Bandwidth validation failed!\n",
__func__,
context->streams[0]->timing.h_addressable,
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
@@ -583,7 +583,7 @@ static uint32_t dce110_timing_generator_
static bool dce110_timing_generator_v_did_triggered_reset_occur(
struct timing_generator *tg)
{
- dm_logger_write(tg->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(tg->ctx->logger,
"Timing Sync not supported on underlay pipe\n");
return false;
}
@@ -592,7 +592,7 @@ static void dce110_timing_generator_v_se
struct timing_generator *tg,
const struct dcp_gsl_params *gsl_params)
{
- dm_logger_write(tg->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(tg->ctx->logger,
"Timing Sync not supported on underlay pipe\n");
return;
}
@@ -601,7 +601,7 @@ static void dce110_timing_generator_v_en
struct timing_generator *tg,
int source_tg_inst)
{
- dm_logger_write(tg->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(tg->ctx->logger,
"Timing Sync not supported on underlay pipe\n");
return;
}
@@ -609,7 +609,7 @@ static void dce110_timing_generator_v_en
static void dce110_timing_generator_v_disable_reset_trigger(
struct timing_generator *tg)
{
- dm_logger_write(tg->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(tg->ctx->logger,
"Timing Sync not supported on underlay pipe\n");
return;
}
@@ -617,7 +617,7 @@ static void dce110_timing_generator_v_di
static void dce110_timing_generator_v_tear_down_global_swap_lock(
struct timing_generator *tg)
{
- dm_logger_write(tg->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(tg->ctx->logger,
"Timing Sync not supported on underlay pipe\n");
return;
}
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
@@ -670,7 +670,7 @@ static void dce110_xfmv_set_pixel_storag
if (!(xfm_dce->lb_pixel_depth_supported & depth)) {
/*we should use unsupported capabilities
* unless it is required by w/a*/
- dm_logger_write(xfm->ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(xfm->ctx->logger,
"%s: Capability not supported",
__func__);
}
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
@@ -129,8 +129,8 @@ static uint32_t lpt_memory_control_confi
LOW_POWER_TILING_NUM_PIPES);
break;
default:
- dm_logger_write(
- cp110->base.ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(
+ cp110->base.ctx->logger,
"%s: Invalid LPT NUM_PIPES!!!",
__func__);
break;
@@ -175,8 +175,8 @@ static uint32_t lpt_memory_control_confi
LOW_POWER_TILING_NUM_BANKS);
break;
default:
- dm_logger_write(
- cp110->base.ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(
+ cp110->base.ctx->logger,
"%s: Invalid LPT NUM_BANKS!!!",
__func__);
break;
@@ -209,8 +209,8 @@ static uint32_t lpt_memory_control_confi
LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
break;
default:
- dm_logger_write(
- cp110->base.ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(
+ cp110->base.ctx->logger,
"%s: Invalid LPT INTERLEAVE_SIZE!!!",
__func__);
break;
@@ -253,15 +253,15 @@ static uint32_t lpt_memory_control_confi
LOW_POWER_TILING_ROW_SIZE);
break;
default:
- dm_logger_write(
- cp110->base.ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(
+ cp110->base.ctx->logger,
"%s: Invalid LPT ROW_SIZE!!!",
__func__);
break;
}
} else {
- dm_logger_write(
- cp110->base.ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(
+ cp110->base.ctx->logger,
"%s: LPT MC Configuration is not provided",
__func__);
}
@@ -311,8 +311,8 @@ static void wait_for_fbc_state_changed(
}
if (counter == 10) {
- dm_logger_write(
- cp110->base.ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(
+ cp110->base.ctx->logger,
"%s: wait counter exceeded, changes to HW not applied",
__func__);
}
@@ -525,8 +525,8 @@ void dce112_compressor_program_compresse
if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
fbc_pitch = fbc_pitch / 8;
else
- dm_logger_write(
- compressor->ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(
+ compressor->ctx->logger,
"%s: Unexpected DCE11 compression ratio",
__func__);
@@ -690,8 +690,8 @@ void dce112_compressor_program_lpt_contr
LOW_POWER_TILING_MODE);
break;
default:
- dm_logger_write(
- compressor->ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(
+ compressor->ctx->logger,
"%s: Invalid selected DRAM channels for LPT!!!",
__func__);
break;
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -722,8 +722,8 @@ bool dce112_validate_bandwidth(
{
bool result = false;
- dm_logger_write(
- dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(
+ dc->ctx->logger,
"%s: start",
__func__);
@@ -737,7 +737,7 @@ bool dce112_validate_bandwidth(
result = true;
if (!result)
- dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
+ DC_LOG_BANDWIDTH_VALIDATION(dc->ctx->logger,
"%s: Bandwidth validation failed!",
__func__);
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -147,7 +147,7 @@ bool hubbub1_verify_allow_pstate_change_
if (debug_data & (1 << 30)) {
if (i > pstate_wait_expected_timeout_us)
- dm_logger_write(hubbub->ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(hubbub->ctx->logger,
"pstate took longer than expected ~%dus\n",
i);
@@ -167,7 +167,7 @@ bool hubbub1_verify_allow_pstate_change_
DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1);
forced_pstate_allow = true;
- dm_logger_write(hubbub->ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(hubbub->ctx->logger,
"pstate TEST_DEBUG_DATA: 0x%X\n",
debug_data);
@@ -211,7 +211,7 @@ void hubbub1_program_watermarks(
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"URGENCY_WATERMARK_A calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->a.urgent_ns, prog_wm_value);
@@ -219,7 +219,7 @@ void hubbub1_program_watermarks(
prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->a.pte_meta_urgent_ns, prog_wm_value);
@@ -229,7 +229,7 @@ void hubbub1_program_watermarks(
watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
@@ -239,7 +239,7 @@ void hubbub1_program_watermarks(
watermarks->a.cstate_pstate.cstate_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"SR_EXIT_WATERMARK_A calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
@@ -249,7 +249,7 @@ void hubbub1_program_watermarks(
watermarks->a.cstate_pstate.pstate_change_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
"HW register value = 0x%x\n\n",
watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
@@ -259,7 +259,7 @@ void hubbub1_program_watermarks(
prog_wm_value = convert_and_clamp(
watermarks->b.urgent_ns, refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"URGENCY_WATERMARK_B calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->b.urgent_ns, prog_wm_value);
@@ -269,7 +269,7 @@ void hubbub1_program_watermarks(
watermarks->b.pte_meta_urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->b.pte_meta_urgent_ns, prog_wm_value);
@@ -280,7 +280,7 @@ void hubbub1_program_watermarks(
watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"SR_ENTER_WATERMARK_B calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
@@ -290,7 +290,7 @@ void hubbub1_program_watermarks(
watermarks->b.cstate_pstate.cstate_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"SR_EXIT_WATERMARK_B calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
@@ -300,7 +300,7 @@ void hubbub1_program_watermarks(
watermarks->b.cstate_pstate.pstate_change_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n"
"HW register value = 0x%x\n",
watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
@@ -309,7 +309,7 @@ void hubbub1_program_watermarks(
prog_wm_value = convert_and_clamp(
watermarks->c.urgent_ns, refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"URGENCY_WATERMARK_C calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->c.urgent_ns, prog_wm_value);
@@ -319,7 +319,7 @@ void hubbub1_program_watermarks(
watermarks->c.pte_meta_urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->c.pte_meta_urgent_ns, prog_wm_value);
@@ -330,7 +330,7 @@ void hubbub1_program_watermarks(
watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"SR_ENTER_WATERMARK_C calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
@@ -340,7 +340,7 @@ void hubbub1_program_watermarks(
watermarks->c.cstate_pstate.cstate_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"SR_EXIT_WATERMARK_C calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
@@ -350,7 +350,7 @@ void hubbub1_program_watermarks(
watermarks->c.cstate_pstate.pstate_change_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n"
"HW register value = 0x%x\n",
watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
@@ -359,7 +359,7 @@ void hubbub1_program_watermarks(
prog_wm_value = convert_and_clamp(
watermarks->d.urgent_ns, refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"URGENCY_WATERMARK_D calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->d.urgent_ns, prog_wm_value);
@@ -368,7 +368,7 @@ void hubbub1_program_watermarks(
watermarks->d.pte_meta_urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->d.pte_meta_urgent_ns, prog_wm_value);
@@ -379,7 +379,7 @@ void hubbub1_program_watermarks(
watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"SR_ENTER_WATERMARK_D calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
@@ -389,7 +389,7 @@ void hubbub1_program_watermarks(
watermarks->d.cstate_pstate.cstate_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"SR_EXIT_WATERMARK_D calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
@@ -400,7 +400,7 @@ void hubbub1_program_watermarks(
watermarks->d.cstate_pstate.pstate_change_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
- dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
"DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
"HW register value = 0x%x\n\n",
watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -359,7 +359,7 @@ static void power_on_plane(
hubp_pg_control(hws, plane_id, true);
REG_SET(DC_IP_REQUEST_CNTL, 0,
IP_REQUEST_EN, 0);
- dm_logger_write(hws->ctx->logger, LOG_DEBUG,
+ DC_LOG_DEBUG(hws->ctx->logger,
"Un-gated front end for pipe %d\n", plane_id);
}
}
@@ -596,7 +596,7 @@ static void reset_back_end_for_pipe(
return;
pipe_ctx->stream = NULL;
- dm_logger_write(dc->ctx->logger, LOG_DEBUG,
+ DC_LOG_DEBUG(dc->ctx->logger,
"Reset back end for pipe %d, tg:%d\n",
pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
}
@@ -656,7 +656,7 @@ static void plane_atomic_power_down(stru
dpp->funcs->dpp_reset(dpp);
REG_SET(DC_IP_REQUEST_CNTL, 0,
IP_REQUEST_EN, 0);
- dm_logger_write(dc->ctx->logger, LOG_DEBUG,
+ DC_LOG_DEBUG(dc->ctx->logger,
"Power gated front end %d\n", pipe_ctx->pipe_idx);
}
}
@@ -703,7 +703,7 @@ static void dcn10_disable_plane(struct d
apply_DEGVIDCN10_253_wa(dc);
- dm_logger_write(dc->ctx->logger, LOG_DC,
+ DC_LOG_DC(dc->ctx->logger,
"Power down front end %d\n",
pipe_ctx->pipe_idx);
}
@@ -1126,7 +1126,7 @@ static void dcn10_enable_per_frame_crtc_
struct dc *core_dc,
struct pipe_ctx *pipe_ctx)
{
- dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
"\n============== DML TTU Output parameters [%d] ==============\n"
"qos_level_low_wm: %d, \n"
"qos_level_high_wm: %d, \n"
@@ -1156,7 +1156,7 @@ static void dcn10_enable_per_frame_crtc_
pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
);
- dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
"\n============== DML DLG Output parameters [%d] ==============\n"
"refcyc_h_blank_end: %d, \n"
"dlg_vblank_end: %d, \n"
@@ -1191,7 +1191,7 @@ static void dcn10_enable_per_frame_crtc_
pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
);
- dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
"\ndst_y_per_meta_row_nom_l: %d, \n"
"refcyc_per_meta_chunk_nom_l: %d, \n"
"refcyc_per_line_delivery_pre_l: %d, \n"
@@ -1221,7 +1221,7 @@ static void dcn10_enable_per_frame_crtc_
pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
);
- dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
"\n============== DML RQ Output parameters [%d] ==============\n"
"chunk_size: %d \n"
"min_chunk_size: %d \n"
@@ -1354,7 +1354,7 @@ static void dcn10_enable_plane(
/* TODO: enable/disable in dm as per update type.
if (plane_state) {
- dm_logger_write(dc->ctx->logger, LOG_DC,
+ DC_LOG_DC(dc->ctx->logger,
"Pipe:%d 0x%x: addr hi:0x%x, "
"addr low:0x%x, "
"src: %d, %d, %d,"
@@ -1372,7 +1372,7 @@ static void dcn10_enable_plane(
plane_state->dst_rect.width,
plane_state->dst_rect.height);
- dm_logger_write(dc->ctx->logger, LOG_DC,
+ DC_LOG_DC(dc->ctx->logger,
"Pipe %d: width, height, x, y format:%d\n"
"viewport:%d, %d, %d, %d\n"
"recout: %d, %d, %d, %d\n",
@@ -1983,7 +1983,7 @@ static void dcn10_apply_ctx_for_surface(
plane_atomic_disconnect(dc, old_pipe_ctx);
removed_pipe[i] = true;
- dm_logger_write(dc->ctx->logger, LOG_DC,
+ DC_LOG_DC(dc->ctx->logger,
"Reset mpcc for pipe %d\n",
old_pipe_ctx->pipe_idx);
}
@@ -2026,7 +2026,7 @@ static void dcn10_apply_ctx_for_surface(
dcn10_verify_allow_pstate_change_high(dc);
}
}
-/* dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+/* DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
"\n============== Watermark parameters ==============\n"
"a.urgent_ns: %d \n"
"a.cstate_enter_plus_exit: %d \n"
@@ -2049,7 +2049,7 @@ static void dcn10_apply_ctx_for_surface(
context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
context->bw.dcn.watermarks.b.pte_meta_urgent_ns
);
- dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
+ DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
"\nc.urgent_ns: %d \n"
"c.cstate_enter_plus_exit: %d \n"
"c.cstate_exit: %d \n"
@@ -2292,7 +2292,7 @@ static void dcn10_wait_for_mpcc_disconne
res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
hubp->funcs->set_blank(hubp, true);
- /*dm_logger_write(dc->ctx->logger, LOG_ERROR,
+ /*DC_LOG_ERROR(dc->ctx->logger,
"[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
i);*/
}
--- a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
@@ -274,7 +274,7 @@ static bool read_command(
if (request->payload.address_space ==
I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
- dm_logger_write(engine->base.ctx->logger, LOG_I2C_AUX, "READ: addr:0x%x value:0x%x Result:%d",
+ DC_LOG_I2C_AUX(engine->base.ctx->logger, "READ: addr:0x%x value:0x%x Result:%d",
request->payload.address,
request->payload.data[0],
ctx.operation_succeeded);
@@ -483,7 +483,7 @@ static bool write_command(
if (request->payload.address_space ==
I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
- dm_logger_write(engine->base.ctx->logger, LOG_I2C_AUX, "WRITE: addr:0x%x value:0x%x Result:%d",
+ DC_LOG_I2C_AUX(engine->base.ctx->logger, "WRITE: addr:0x%x value:0x%x Result:%d",
request->payload.address,
request->payload.data[0],
ctx.operation_succeeded);
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
@@ -525,8 +525,8 @@ static void construct(
REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);
if (xtal_ref_div == 0) {
- dm_logger_write(
- hw_engine->base.base.base.ctx->logger, LOG_WARNING,
+ DC_LOG_WARNING(
+ hw_engine->base.base.base.ctx->logger,
"Invalid base timer divider\n",
__func__);
xtal_ref_div = 2;
--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
@@ -181,8 +181,8 @@ bool dal_irq_service_dummy_set(
const struct irq_source_info *info,
bool enable)
{
- dm_logger_write(
- irq_service->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(
+ irq_service->ctx->logger,
"%s: called for non-implemented irq source\n",
__func__);
return false;
@@ -192,8 +192,8 @@ bool dal_irq_service_dummy_ack(
struct irq_service *irq_service,
const struct irq_source_info *info)
{
- dm_logger_write(
- irq_service->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(
+ irq_service->ctx->logger,
"%s: called for non-implemented irq source\n",
__func__);
return false;
--- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
@@ -104,8 +104,8 @@ bool dal_irq_service_set(
find_irq_source_info(irq_service, source);
if (!info) {
- dm_logger_write(
- irq_service->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(
+ irq_service->ctx->logger,
"%s: cannot find irq info table entry for %d\n",
__func__,
source);
@@ -142,8 +142,8 @@ bool dal_irq_service_ack(
find_irq_source_info(irq_service, source);
if (!info) {
- dm_logger_write(
- irq_service->ctx->logger, LOG_ERROR,
+ DC_LOG_ERROR(
+ irq_service->ctx->logger,
"%s: cannot find irq info table entry for %d\n",
__func__,
source);
--- a/drivers/gpu/drm/amd/display/include/logger_types.h
+++ b/drivers/gpu/drm/amd/display/include/logger_types.h
@@ -29,6 +29,39 @@
#include "os_types.h"
#define MAX_NAME_LEN 32
+#define DC_LOG_ERROR(a, b, ...) dm_logger_write(a, LOG_ERROR, b, ## __VA_ARGS__)
+#define DC_LOG_WARNING(a, b, ...) dm_logger_write(a, LOG_WARNING, b, ## __VA_ARGS__)
+#define DC_LOG_DEBUG(a, b, ...) dm_logger_write(a, LOG_DEBUG, b, ## __VA_ARGS__)
+#define DC_LOG_DC(a, b, ...) dm_logger_write(a, LOG_DC, b, ## __VA_ARGS__)
+#define DC_LOG_DTN(a, b, ...) dm_logger_write(a, LOG_DTN, b, ## __VA_ARGS__)
+#define DC_LOG_SURFACE(a, b, ...) dm_logger_write(a, LOG_SURFACE, b, ## __VA_ARGS__)
+#define DC_LOG_HW_HOTPLUG(a, b, ...) dm_logger_write(a, LOG_HW_HOTPLUG, b, ## __VA_ARGS__)
+#define DC_LOG_HW_LINK_TRAINING(a, b, ...) dm_logger_write(a, LOG_HW_LINK_TRAINING, b, ## __VA_ARGS__)
+#define DC_LOG_HW_SET_MODE(a, b, ...) dm_logger_write(a, LOG_HW_SET_MODE, b, ## __VA_ARGS__)
+#define DC_LOG_HW_RESUME_S3(a, b, ...) dm_logger_write(a, LOG_HW_RESUME_S3, b, ## __VA_ARGS__)
+#define DC_LOG_HW_AUDIO(a, b, ...) dm_logger_write(a, LOG_HW_AUDIO, b, ## __VA_ARGS__)
+#define DC_LOG_HW_HPD_IRQ(a, b, ...) dm_logger_write(a, LOG_HW_HPD_IRQ, b, ## __VA_ARGS__)
+#define DC_LOG_MST(a, b, ...) dm_logger_write(a, LOG_MST, b, ## __VA_ARGS__)
+#define DC_LOG_SCALER(a, b, ...) dm_logger_write(a, LOG_SCALER, b, ## __VA_ARGS__)
+#define DC_LOG_BIOS(a, b, ...) dm_logger_write(a, LOG_BIOS, b, ## __VA_ARGS__)
+#define DC_LOG_BANDWIDTH_CALCS(a, b, ...) dm_logger_write(a, LOG_BANDWIDTH_CALCS, b, ## __VA_ARGS__)
+#define DC_LOG_BANDWIDTH_VALIDATION(a, b, ...) dm_logger_write(a, LOG_BANDWIDTH_VALIDATION, b, ## __VA_ARGS__)
+#define DC_LOG_I2C_AUX(a, b, ...) dm_logger_write(a, LOG_I2C_AUX, b, ## __VA_ARGS__)
+#define DC_LOG_SYNC(a, b, ...) dm_logger_write(a, LOG_SYNC, b, ## __VA_ARGS__)
+#define DC_LOG_BACKLIGHT(a, b, ...) dm_logger_write(a, LOG_BACKLIGHT, b, ## __VA_ARGS__)
+#define DC_LOG_FEATURE_OVERRIDE(a, b, ...) dm_logger_write(a, LOG_FEATURE_OVERRIDE, b, ## __VA_ARGS__)
+#define DC_LOG_DETECTION_EDID_PARSER(a, b, ...) dm_logger_write(a, LOG_DETECTION_EDID_PARSER, b, ## __VA_ARGS__)
+#define DC_LOG_DETECTION_DP_CAPS(a, b, ...) dm_logger_write(a, LOG_DETECTION_DP_CAPS, b, ## __VA_ARGS__)
+#define DC_LOG_RESOURCE(a, b, ...) dm_logger_write(a, LOG_RESOURCE, b, ## __VA_ARGS__)
+#define DC_LOG_DML(a, b, ...) dm_logger_write(a, LOG_DML, b, ## __VA_ARGS__)
+#define DC_LOG_EVENT_MODE_SET(a, b, ...) dm_logger_write(a, LOG_EVENT_MODE_SET, b, ## __VA_ARGS__)
+#define DC_LOG_EVENT_DETECTION(a, b, ...) dm_logger_write(a, LOG_EVENT_DETECTION, b, ## __VA_ARGS__)
+#define DC_LOG_EVENT_LINK_TRAINING(a, b, ...) dm_logger_write(a, LOG_EVENT_LINK_TRAINING, b, ## __VA_ARGS__)
+#define DC_LOG_EVENT_LINK_LOSS(a, b, ...) dm_logger_write(a, LOG_EVENT_LINK_LOSS, b, ## __VA_ARGS__)
+#define DC_LOG_EVENT_UNDERFLOW(a, b, ...) dm_logger_write(a, LOG_EVENT_UNDERFLOW, b, ## __VA_ARGS__)
+#define DC_LOG_IF_TRACE(a, b, ...) dm_logger_write(a, LOG_IF_TRACE, b, ## __VA_ARGS__)
+#define DC_LOG_PERF_TRACE(a, b, ...) dm_logger_write(a, LOG_PERF_TRACE, b, ## __VA_ARGS__)
+
struct dal_logger;