From: Rex Zhu <Rex.Zhu@amd.com>
Date: Thu, 15 Mar 2018 14:45:04 +0800
Subject: drm/amd/pp: Remove the cgs wrapper for notify smu version on APU
Git-commit: 59156faf810e05f5c5241f9a90e6d715d1185cd1
Patch-mainline: v4.17-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
Refine commit f49e9bac191b ("drm/amd/pp: Get and save Rv smu version")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 5 -----
drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 6 ++----
drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 6 +++---
3 files changed, 5 insertions(+), 12 deletions(-)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -654,11 +654,6 @@ static int amdgpu_cgs_get_firmware_info(
else
strcpy(fw_name, "amdgpu/vega10_smc.bin");
break;
- case CHIP_CARRIZO:
- case CHIP_STONEY:
- case CHIP_RAVEN:
- adev->pm.fw_version = info->version;
- return 0;
default:
DRM_ERROR("SMC firmware not supported\n");
return -EINVAL;
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
@@ -247,13 +247,11 @@ static int smu10_smu_fini(struct pp_hwmg
static int smu10_start_smu(struct pp_hwmgr *hwmgr)
{
- struct cgs_firmware_info info = {0};
+ struct amdgpu_device *adev = hwmgr->adev;
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
hwmgr->smu_version = smu10_read_arg_from_smc(hwmgr);
- info.version = hwmgr->smu_version >> 8;
-
- cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
+ adev->pm.fw_version = hwmgr->smu_version >> 8;
if (smu10_verify_smc_interface(hwmgr))
return -EINVAL;
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
@@ -698,7 +698,8 @@ static int smu8_start_smu(struct pp_hwmg
{
int ret = 0;
uint32_t fw_to_check = 0;
- struct cgs_firmware_info info = {0};
+ struct amdgpu_device *adev = hwmgr->adev;
+
uint32_t index = SMN_MP1_SRAM_START_ADDR +
SMU8_FIRMWARE_HEADER_LOCATION +
offsetof(struct SMU8_Firmware_Header, Version);
@@ -709,8 +710,7 @@ static int smu8_start_smu(struct pp_hwmg
cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA);
- info.version = hwmgr->smu_version >> 8;
- cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
+ adev->pm.fw_version = hwmgr->smu_version >> 8;
fw_to_check = UCODE_ID_RLC_G_MASK |
UCODE_ID_SDMA0_MASK |