From: Ben Skeggs <bskeggs@redhat.com>
Date: Tue, 8 May 2018 20:39:46 +1000
Subject: drm/nouveau/gr/gf100-: virtualise r4060a8 + apply fixes from traces
Git-commit: 9d8a80df73b58c700e36a0051b2fb44f252693e2
Patch-mainline: v4.18-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

Also fixes some GPUs where we write too many registers.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c |   11 ++++++++---
 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h |    3 ++-
 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c |    1 +
 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c |    1 +
 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c |    1 +
 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c |    2 +-
 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c |    1 +
 7 files changed, 15 insertions(+), 5 deletions(-)

--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
@@ -1083,7 +1083,9 @@ void
 gf100_grctx_generate_r4060a8(struct gf100_gr *gr)
 {
 	struct nvkm_device *device = gr->base.engine.subdev.device;
-	u8  tpcnr[GPC_MAX], data[TPC_MAX];
+	const u8 gpcmax = nvkm_rd32(device, 0x022430);
+	const u8 tpcmax = nvkm_rd32(device, 0x022434) * gpcmax;
+	u8 tpcnr[GPC_MAX], data[TPC_MAX];
 	int gpc, tpc, i;
 
 	memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
@@ -1098,7 +1100,7 @@ gf100_grctx_generate_r4060a8(struct gf10
 		data[tpc] = gpc;
 	}
 
-	for (i = 0; i < 4; i++)
+	for (i = 0; i < DIV_ROUND_UP(tpcmax, 4); i++)
 		nvkm_wr32(device, 0x4060a8 + (i * 4), ((u32 *)data)[i]);
 }
 
@@ -1236,6 +1238,9 @@ gf100_grctx_generate_floorsweep(struct g
 		nvkm_wr32(device, 0x406028 + (i * 4), data);
 		nvkm_wr32(device, 0x405870 + (i * 4), data);
 	}
+
+	if (func->r4060a8)
+		func->r4060a8(gr);
 }
 
 void
@@ -1267,7 +1272,6 @@ gf100_grctx_generate_main(struct gf100_g
 	grctx->unkn(gr);
 
 	gf100_grctx_generate_floorsweep(gr);
-	gf100_grctx_generate_r4060a8(gr);
 	gf100_grctx_generate_r418bb8(gr);
 	gf100_grctx_generate_r406800(gr);
 
@@ -1419,4 +1423,5 @@ gf100_grctx = {
 	.attrib_nr = 0x218,
 	.sm_id = gf100_grctx_generate_sm_id,
 	.tpc_nr = gf100_grctx_generate_tpc_nr,
+	.r4060a8 = gf100_grctx_generate_r4060a8,
 };
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
@@ -52,6 +52,7 @@ struct gf100_grctx_func {
 	/* floorsweeping */
 	void (*sm_id)(struct gf100_gr *, int gpc, int tpc, int sm);
 	void (*tpc_nr)(struct gf100_gr *, int gpc);
+	void (*r4060a8)(struct gf100_gr *);
 };
 
 extern const struct gf100_grctx_func gf100_grctx;
@@ -62,11 +63,11 @@ void gf100_grctx_generate_pagepool(struc
 void gf100_grctx_generate_attrib(struct gf100_grctx *);
 void gf100_grctx_generate_unkn(struct gf100_gr *);
 void gf100_grctx_generate_floorsweep(struct gf100_gr *);
-void gf100_grctx_generate_r4060a8(struct gf100_gr *);
 void gf100_grctx_generate_r418bb8(struct gf100_gr *);
 void gf100_grctx_generate_r406800(struct gf100_gr *);
 void gf100_grctx_generate_sm_id(struct gf100_gr *, int, int, int);
 void gf100_grctx_generate_tpc_nr(struct gf100_gr *, int);
+void gf100_grctx_generate_r4060a8(struct gf100_gr *);
 
 extern const struct gf100_grctx_func gf108_grctx;
 void gf108_grctx_generate_attrib(struct gf100_grctx *);
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c
@@ -98,4 +98,5 @@ gf104_grctx = {
 	.attrib_nr = 0x218,
 	.sm_id = gf100_grctx_generate_sm_id,
 	.tpc_nr = gf100_grctx_generate_tpc_nr,
+	.r4060a8 = gf100_grctx_generate_r4060a8,
 };
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c
@@ -796,4 +796,5 @@ gf108_grctx = {
 	.alpha_nr = 0x218,
 	.sm_id = gf100_grctx_generate_sm_id,
 	.tpc_nr = gf100_grctx_generate_tpc_nr,
+	.r4060a8 = gf100_grctx_generate_r4060a8,
 };
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c
@@ -349,4 +349,5 @@ gf110_grctx = {
 	.attrib_nr = 0x218,
 	.sm_id = gf100_grctx_generate_sm_id,
 	.tpc_nr = gf100_grctx_generate_tpc_nr,
+	.r4060a8 = gf100_grctx_generate_r4060a8,
 };
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
@@ -241,7 +241,6 @@ gf117_grctx_generate_main(struct gf100_g
 	grctx->unkn(gr);
 
 	gf100_grctx_generate_floorsweep(gr);
-	gf100_grctx_generate_r4060a8(gr);
 	gk104_grctx_generate_r418bb8(gr);
 	gf100_grctx_generate_r406800(gr);
 
@@ -276,4 +275,5 @@ gf117_grctx = {
 	.alpha_nr = 0x324,
 	.sm_id = gf100_grctx_generate_sm_id,
 	.tpc_nr = gf100_grctx_generate_tpc_nr,
+	.r4060a8 = gf100_grctx_generate_r4060a8,
 };
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c
@@ -519,4 +519,5 @@ gf119_grctx = {
 	.alpha_nr = 0x218,
 	.sm_id = gf100_grctx_generate_sm_id,
 	.tpc_nr = gf100_grctx_generate_tpc_nr,
+	.r4060a8 = gf100_grctx_generate_r4060a8,
 };