From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Wed, 2 May 2018 14:58:51 -0700
Subject: drm/i915: enable the pipe/transcoder/planes later on HSW+
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Git-commit: c8af5274c3cbacb0905a26bcdef85901216e1134
Patch-mainline: v4.19-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
For all platforms that run haswell_crtc_enable, our spec tells us to
configure the transcoder clocks and do link training before it tells
us to set pipeconf and the other pipe/transcoder/plane registers.
Starting from Icelake, we get machine hangs if we try to touch the
pipe/transcoder registers without having the clocks configured and not
having some chicken bits set. So this patch changes
haswell_crtc_enable() to issue the calls at the appropriate order
mandated by the spec.
While setting the appropriate chicken bits would also work here, it's
better if we actually program the hardware the way it is intended to
be programmed. And the chicken bit also has some theoretical downsides
that may or may not affect us. Also, correctly programming the
hardware does not prevent us from setting the chicken bits in a later
patch in case we decide to.
v2: Don't forget link training (Ville).
Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180502215851.30736-1-paulo.r.zanoni@intel.com
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5576,6 +5576,11 @@ static void haswell_crtc_enable(struct i
if (INTEL_GEN(dev_priv) >= 11)
icl_map_plls_to_ports(crtc, pipe_config, old_state);
+ intel_encoders_pre_enable(crtc, pipe_config, old_state);
+
+ if (!transcoder_is_dsi(cpu_transcoder))
+ intel_ddi_enable_pipe_clock(pipe_config);
+
if (intel_crtc_has_dp_encoder(intel_crtc->config))
intel_dp_set_m_n(intel_crtc, M1_N1);
@@ -5604,11 +5609,6 @@ static void haswell_crtc_enable(struct i
intel_crtc->active = true;
- intel_encoders_pre_enable(crtc, pipe_config, old_state);
-
- if (!transcoder_is_dsi(cpu_transcoder))
- intel_ddi_enable_pipe_clock(pipe_config);
-
/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
intel_crtc->config->pch_pfit.enabled;