From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu, 31 May 2018 09:22:45 +0100
Subject: drm/i915: After reset on sanitization, reset the engine backends
Git-commit: c3160da9a6af0e2d8f4fb3410df9d027a178ca3d
Patch-mainline: v4.19-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
As we reset the GPU on suspend/resume, we also do need to reset the
engine state tracking so call into the engine backends. This is
especially important so that we can also sanitize the state tracking
across resume.
References: https://bugs.freedesktop.org/show_bug.cgi?id=106702
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180531082246.9763-3-chris@chris-wilson.co.uk
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/i915/i915_gem.c | 24 ++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_lrc.c | 8 +++++---
2 files changed, 29 insertions(+), 3 deletions(-)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4987,7 +4987,22 @@ static void assert_kernel_context_is_cur
void i915_gem_sanitize(struct drm_i915_private *i915)
{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ GEM_TRACE("\n");
+
mutex_lock(&i915->drm.struct_mutex);
+
+ intel_runtime_pm_get(i915);
+ intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
+
+ /*
+ * As we have just resumed the machine and woken the device up from
+ * deep PCI sleep (presumably D3_cold), assume the HW has been reset
+ * back to defaults, recovering from whatever wedged state we left it
+ * in and so worth trying to use the device once more.
+ */
if (i915_terminally_wedged(&i915->gpu_error))
i915_gem_unset_wedged(i915);
@@ -5002,6 +5017,15 @@ void i915_gem_sanitize(struct drm_i915_p
if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915))
WARN_ON(intel_gpu_reset(i915, ALL_ENGINES));
+ /* Reset the submission backend after resume as well as the GPU reset */
+ for_each_engine(engine, i915, id) {
+ if (engine->reset.reset)
+ engine->reset.reset(engine, NULL);
+ }
+
+ intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
+ intel_runtime_pm_put(i915);
+
i915_gem_contexts_lost(i915);
mutex_unlock(&i915->drm.struct_mutex);
}
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1797,9 +1797,6 @@ static void enable_execlists(struct inte
I915_WRITE(RING_HWS_PGA(engine->mmio_base),
engine->status_page.ggtt_offset);
POSTING_READ(RING_HWS_PGA(engine->mmio_base));
-
- /* Following the reset, we need to reload the CSB read/write pointers */
- engine->execlists.csb_head = -1;
}
static bool unexpected_starting_state(struct intel_engine_cs *engine)
@@ -1971,6 +1968,9 @@ static void execlists_reset(struct intel
__unwind_incomplete_requests(engine);
spin_unlock(&engine->timeline.lock);
+ /* Following the reset, we need to reload the CSB read/write pointers */
+ engine->execlists.csb_head = -1;
+
local_irq_restore(flags);
/*
@@ -2470,6 +2470,8 @@ static int logical_ring_init(struct inte
upper_32_bits(ce->lrc_desc);
}
+ engine->execlists.csb_head = -1;
+
return 0;
error: