From: Mikita Lipski <mikita.lipski@amd.com>
Date: Thu, 31 May 2018 17:31:14 -0400
Subject: drm/amd/display: Add dmpp clks types for conversion
Git-commit: 015ec75918698e63f770c9bee0752ce802ed55e2
Patch-mainline: v4.19-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

Add more cases for dm_pp clks translator into pp clks so
we can pass the right structures to the powerplay.
Use clks translator instead of massive switch statement.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c |   41 +++++--------
 1 file changed, 18 insertions(+), 23 deletions(-)

--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -195,6 +195,21 @@ static enum amd_pp_clock_type dc_to_pp_c
 	case DM_PP_CLOCK_TYPE_MEMORY_CLK:
 		amd_pp_clk_type = amd_pp_mem_clock;
 		break;
+	case DM_PP_CLOCK_TYPE_DCEFCLK:
+		amd_pp_clk_type  = amd_pp_dcef_clock;
+		break;
+	case DM_PP_CLOCK_TYPE_DCFCLK:
+		amd_pp_clk_type = amd_pp_dcf_clock;
+		break;
+	case DM_PP_CLOCK_TYPE_PIXELCLK:
+		amd_pp_clk_type = amd_pp_pixel_clock;
+		break;
+	case DM_PP_CLOCK_TYPE_FCLK:
+		amd_pp_clk_type = amd_pp_f_clock;
+		break;
+	case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
+		amd_pp_clk_type = amd_pp_dpp_clock;
+		break;
 	default:
 		DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
 				dm_pp_clk_type);
@@ -424,32 +439,12 @@ bool dm_pp_apply_clock_for_voltage_reque
 	struct amdgpu_device *adev = ctx->driver_context;
 	struct pp_display_clock_request pp_clock_request = {0};
 	int ret = 0;
-	switch (clock_for_voltage_req->clk_type) {
-	case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
-		pp_clock_request.clock_type = amd_pp_disp_clock;
-		break;
-
-	case DM_PP_CLOCK_TYPE_DCEFCLK:
-		pp_clock_request.clock_type = amd_pp_dcef_clock;
-		break;
 
-	case DM_PP_CLOCK_TYPE_DCFCLK:
-		pp_clock_request.clock_type = amd_pp_dcf_clock;
-		break;
-
-	case DM_PP_CLOCK_TYPE_PIXELCLK:
-		pp_clock_request.clock_type = amd_pp_pixel_clock;
-		break;
-
-	case DM_PP_CLOCK_TYPE_FCLK:
-		pp_clock_request.clock_type = amd_pp_f_clock;
-		break;
+	pp_clock_request.clock_type = dc_to_pp_clock_type(clock_for_voltage_req->clk_type);
+	pp_clock_request.clock_freq_in_khz = clock_for_voltage_req->clocks_in_khz;
 
-	default:
+	if (!pp_clock_request.clock_type)
 		return false;
-	}
-
-	pp_clock_request.clock_freq_in_khz = clock_for_voltage_req->clocks_in_khz;
 
 	if (adev->powerplay.pp_funcs->display_clock_voltage_request)
 		ret = adev->powerplay.pp_funcs->display_clock_voltage_request(