From c00054f540bf81e592e1fee709b0bdbf20f478b5 Mon Sep 17 00:00:00 2001
From: Bjorn Helgaas <bhelgaas@google.com>
Date: Mon, 13 Nov 2017 15:05:50 -0600
Subject: [PATCH] PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD
Git-commit: c00054f540bf81e592e1fee709b0bdbf20f478b5
Patch-mainline: v4.15-rc1
References: bsc#1051510
Previously we programmed the LTR_L1.2_THRESHOLD in the parent (upstream)
device using the capability pointer of the *child* (downstream) device,
which corrupted some random word of the parent's config space.
Use the parent's L1 SS capability pointer to program its
LTR_L1.2_THRESHOLD.
Fixes: aeda9adebab8 ("PCI/ASPM: Configure L1 substate settings")
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Cc: stable@vger.kernel.org # v4.11+
Cc: Rajat Jain <rajatja@google.com>
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/pci/pcie/aspm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -657,7 +657,7 @@ static void pcie_config_aspm_l1ss(struct
0xFF00, link->l1ss.ctl1);
/* Program LTR L1.2 threshold in both ports */
- pci_clear_and_set_dword(parent, dw_cap_ptr + PCI_L1SS_CTL1,
+ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
0xE3FF0000, link->l1ss.ctl1);
pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
0xE3FF0000, link->l1ss.ctl1);