From: Yixian Liu <liuyixian@huawei.com>
Date: Fri, 29 Dec 2017 19:26:18 +0800
Subject: RDMA/hns: Add detailed comments for mb() call
Patch-mainline: v4.16-rc1
Git-commit: 4044a3f482a3373ea5379da47c04ebecb9a3f133
References: bsc#1104427 FATE#326416
This patch adds more detailed comments when we call the
memory barrier function, such as rmb, wmb and mb. Three
mb() callers are deleted since they are unnecessary.
Suggested-by: Jason Gunthorpe <jgg@mellanox.com>
Signed-off-by: Yixian Liu <liuyixian@huawei.com>
Signed-off-by: Lijun Ou <oulijun@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
Reviewed-by: Leon Romanovsky <leonro@mellanox.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
---
drivers/infiniband/hw/hns/hns_roce_hw_v1.c | 19 ++++++++++++-------
drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 26 ++++++++++----------------
2 files changed, 22 insertions(+), 23 deletions(-)
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
@@ -3963,8 +3963,6 @@ static void set_eq_cons_index_v1(struct
{
roce_raw_write((eq->cons_index & HNS_ROCE_V1_CONS_IDX_M) |
(req_not << eq->log_entries), eq->doorbell);
- /* Memory barrier */
- mb();
}
static void hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
@@ -4156,13 +4154,16 @@ static int hns_roce_v1_aeq_int(struct hn
int event_type;
while ((aeqe = next_aeqe_sw_v1(eq))) {
+
+ /* Make sure we read the AEQ entry after we have checked the
+ * ownership bit
+ */
+ dma_rmb();
+
dev_dbg(dev, "aeqe = %p, aeqe->asyn.event_type = 0x%lx\n", aeqe,
roce_get_field(aeqe->asyn,
HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
- /* Memory barrier */
- rmb();
-
event_type = roce_get_field(aeqe->asyn,
HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S);
@@ -4260,8 +4261,12 @@ static int hns_roce_v1_ceq_int(struct hn
u32 cqn;
while ((ceqe = next_ceqe_sw_v1(eq))) {
- /* Memory barrier */
- rmb();
+
+ /* Make sure we read CEQ entry after we have checked the
+ * ownership bit
+ */
+ dma_rmb();
+
cqn = roce_get_field(ceqe->comp,
HNS_ROCE_CEQE_CEQE_COMP_CQN_M,
HNS_ROCE_CEQE_CEQE_COMP_CQN_S);
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -3207,10 +3207,6 @@ static void set_eq_cons_index_v2(struct
(eq->cons_index & HNS_ROCE_V2_CONS_IDX_M));
hns_roce_write64_k(doorbell, eq->doorbell);
-
- /* Memory barrier */
- mb();
-
}
static void hns_roce_v2_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
@@ -3392,8 +3388,11 @@ static int hns_roce_v2_aeq_int(struct hn
int event_type;
while ((aeqe = next_aeqe_sw_v2(eq))) {
- /* Memory barrier */
- rmb();
+
+ /* Make sure we read AEQ entry after we have checked the
+ * ownership bit
+ */
+ dma_rmb();
event_type = roce_get_field(aeqe->asyn,
HNS_ROCE_V2_AEQE_EVENT_TYPE_M,
@@ -3508,8 +3507,11 @@ static int hns_roce_v2_ceq_int(struct hn
while ((ceqe = next_ceqe_sw_v2(eq))) {
- /* Memory barrier */
- rmb();
+ /* Make sure we read CEQ entry after we have checked the
+ * ownership bit
+ */
+ dma_rmb();
+
cqn = roce_get_field(ceqe->comp,
HNS_ROCE_V2_CEQE_COMP_CQN_M,
HNS_ROCE_V2_CEQE_COMP_CQN_S);
@@ -3564,9 +3566,6 @@ static irqreturn_t hns_roce_v2_msix_inte
roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S, 1);
roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
- /* Memory barrier */
- mb();
-
roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
@@ -3577,9 +3576,6 @@ static irqreturn_t hns_roce_v2_msix_inte
roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S, 1);
roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
- /* Memory barrier */
- mb();
-
roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
@@ -3590,8 +3586,6 @@ static irqreturn_t hns_roce_v2_msix_inte
roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S, 1);
roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
- /* Memory barrier */
- mb();
roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);