From: Marc Zyngier <marc.zyngier@arm.com>
Date: Thu, 23 May 2019 11:24:50 +0100
Subject: arm64: Handle erratum 1418040 as a superset of erratum 1188873
Git-commit: a5325089bd05a7b0259cc4038479d36308edbda2
Patch-mainline: v5.2-rc2
References: jsc#ECO-561
We already mitigate erratum 1188873 affecting Cortex-A76 and
Neoverse-N1 r0p0 to r2p0. It turns out that revisions r0p0 to
r3p1 of the same cores are affected by erratum 1418040, which
has the same workaround as 1188873.
Let's expand the range of affected revisions to match 1418040,
and repaint all occurences of 1188873 to 1418040. Whilst we're
there, do a bit of reformating in silicon-errata.txt and drop
a now unnecessary dependency on ARM_ARCH_TIMER_OOL_WORKAROUND.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
---
Documentation/arm64/silicon-errata.txt | 8 ++++----
arch/arm64/Kconfig | 7 +++----
arch/arm64/include/asm/cpucaps.h | 2 +-
arch/arm64/kernel/cpu_errata.c | 24 ++++++++++++++----------
arch/arm64/kernel/entry.S | 4 ++--
5 files changed, 24 insertions(+), 21 deletions(-)
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -56,11 +56,11 @@ stable kernels.
| ARM | Cortex-A72 | #853709 | N/A |
| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
-| ARM | Cortex-A76 | #1188873 | ARM64_ERRATUM_1188873 |
-| ARM | Neoverse-N1 | #1188873 | ARM64_ERRATUM_1188873 |
-| ARM | MMU-500 | #841119,#826419 | N/A |
+| ARM | Cortex-A76 | #1188873,1418040| ARM64_ERRATUM_1418040 |
+| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
+| ARM | MMU-500 | #841119,826419 | N/A |
| | | | |
-| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
+| Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 |
| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -461,16 +461,15 @@ config ARM64_ERRATUM_1024718
If unsure, say Y.
-config ARM64_ERRATUM_1188873
+config ARM64_ERRATUM_1418040
bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
default y
depends on COMPAT
- select ARM_ARCH_TIMER_OOL_WORKAROUND
help
This option adds work arounds for ARM Cortex-A76/Neoverse-N1
- erratum 1188873
+ errata 1188873 and 1418040.
- Affected Cortex-A76/Neoverse-N1 cores (r0p0, r1p0, r2p0) could
+ Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
cause register corruption when accessing the timer registers
from AArch32 userspace.
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -49,7 +49,7 @@
#define ARM64_HAS_CNP 28
#define ARM64_WORKAROUND_843419 29
#define ARM64_SSBS 30
-#define ARM64_WORKAROUND_1188873 31
+#define ARM64_WORKAROUND_1418040 31
#define ARM64_HAS_CACHE_IDC 32
#define ARM64_HAS_CACHE_DIC 33
#define ARM64_MISMATCHED_CACHE_TYPE 34
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -649,12 +649,16 @@ static const struct midr_range workaroun
};
#endif
-#ifdef CONFIG_ARM64_ERRATUM_1188873
-static const struct midr_range erratum_1188873_list[] = {
- /* Cortex-A76 r0p0 to r2p0 */
- MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
- /* Neoverse-N1 r0p0 to r2p0 */
- MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 2, 0),
+#ifdef CONFIG_ARM64_ERRATUM_1418040
+/*
+ * - 1188873 affects r0p0 to r2p0
+ * - 1418040 affects r0p0 to r3p1
+ */
+static const struct midr_range erratum_1418040_list[] = {
+ /* Cortex-A76 r0p0 to r3p1 */
+ MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
+ /* Neoverse-N1 r0p0 to r3p1 */
+ MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
{},
};
#endif
@@ -768,11 +772,11 @@ const struct arm64_cpu_capabilities arm6
.matches = has_ssbd_mitigation,
.midr_range_list = arm64_ssb_cpus,
},
-#ifdef CONFIG_ARM64_ERRATUM_1188873
+#ifdef CONFIG_ARM64_ERRATUM_1418040
{
- .desc = "ARM erratum 1188873",
- .capability = ARM64_WORKAROUND_1188873,
- ERRATA_MIDR_RANGE_LIST(erratum_1188873_list),
+ .desc = "ARM erratum 1418040",
+ .capability = ARM64_WORKAROUND_1418040,
+ ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
},
#endif
{
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -330,8 +330,8 @@ alternative_if ARM64_WORKAROUND_845719
alternative_else_nop_endif
#endif
3:
-#ifdef CONFIG_ARM64_ERRATUM_1188873
-alternative_if_not ARM64_WORKAROUND_1188873
+#ifdef CONFIG_ARM64_ERRATUM_1418040
+alternative_if_not ARM64_WORKAROUND_1418040
b 4f
alternative_else_nop_endif
/*