From: Michael Chan <michael.chan@broadcom.com>
Date: Fri, 3 Nov 2017 03:32:39 -0400
Subject: bnxt_en: Fix IRQ coalescing regression.
Patch-mainline: v4.15-rc1
Git-commit: b153cbc507946f52d5aa687fd64f45d82cb36a3b
References: bsc#1050242 FATE#322914

Recent IRQ coalescing clean up has removed a guard-rail for the max DMA
buffer coalescing value.  This is a 6-bit value and must not be 0.  We
already have a check for 0 but 64 is equivalent to 0 and will cause
non-stop interrupts.  Fix it by adding the proper check.

Fixes: f8503969d27b ("bnxt_en: Refactor and simplify coalescing code.")
Reported-by: Andy Gospodarek <gospo@broadcom.com>
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
---
 drivers/net/ethernet/broadcom/bnxt/bnxt.c |    6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
@@ -4548,9 +4548,13 @@ static void bnxt_hwrm_set_coal_params(st
 
 	val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
 	req->num_cmpl_aggr_int = cpu_to_le16(val);
+
+	/* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
+	val = min_t(u16, val, 63);
 	req->num_cmpl_dma_aggr = cpu_to_le16(val);
 
-	val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, max);
+	/* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
+	val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 63);
 	req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
 
 	tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks);