From 0e8e4fbf8d8905071c045f2922de55adbe1a6abe Mon Sep 17 00:00:00 2001
From: Hersen Wu <hersenxs.wu@amd.com>
Date: Tue, 21 Aug 2018 09:35:47 -0400
Subject: [PATCH] drm/amd/display: num of sw i2c/aux engines less than num of connectors
Git-commit: 0e8e4fbf8d8905071c045f2922de55adbe1a6abe
Patch-mainline: v4.20-rc1
References: bsc#1145946
[why]
AMD Stoney reference board, there are only 2 pipes (not include
underlay), and 3 connectors. resource creation, only
2 I2C/AUX engines are created. Within dc_link_aux_transfer, when
pin_data_en =2, refer to enengines[ddc_pin->pin_data->en] = NULL.
NULL point is referred later causing system crash.
[how]
each asic design has fixed number of ddc engines at hw side.
for each ddc engine, create its i2x/aux engine at sw side.
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 6 +++
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 4 ++
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 5 +++
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 10 ++++--
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 25 ++++++++++++++++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 8 +++--
drivers/gpu/drm/amd/display/dc/inc/resource.h | 1
7 files changed, 52 insertions(+), 7 deletions(-)
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -371,7 +371,8 @@ static const struct resource_caps res_ca
.num_timing_generator = 6,
.num_audio = 6,
.num_stream_encoder = 6,
- .num_pll = 3
+ .num_pll = 3,
+ .num_ddc = 6,
};
#define CTX ctx
@@ -963,6 +964,9 @@ static bool construct(
"DC: failed to create output pixel processor!\n");
goto res_create_fail;
}
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -377,6 +377,7 @@ static const struct resource_caps carriz
.num_audio = 3,
.num_stream_encoder = 3,
.num_pll = 2,
+ .num_ddc = 3,
};
static const struct resource_caps stoney_resource_cap = {
@@ -385,6 +386,7 @@ static const struct resource_caps stoney
.num_audio = 3,
.num_stream_encoder = 3,
.num_pll = 2,
+ .num_ddc = 3,
};
#define CTX ctx
@@ -1295,7 +1297,9 @@ static bool construct(
"DC: failed to create output pixel processor!\n");
goto res_create_fail;
}
+ }
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce110_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -383,6 +383,7 @@ static const struct resource_caps polari
.num_audio = 6,
.num_stream_encoder = 6,
.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
+ .num_ddc = 6,
};
static const struct resource_caps polaris_11_resource_cap = {
@@ -390,6 +391,7 @@ static const struct resource_caps polari
.num_audio = 5,
.num_stream_encoder = 5,
.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
+ .num_ddc = 5,
};
#define CTX ctx
@@ -1245,6 +1247,9 @@ static bool construct(
"DC:failed to create output pixel processor!\n");
goto res_create_fail;
}
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -402,6 +402,7 @@ static const struct resource_caps res_ca
.num_audio = 7,
.num_stream_encoder = 6,
.num_pll = 6,
+ .num_ddc = 6,
};
static const struct dc_debug_options debug_defaults = {
@@ -1020,6 +1021,12 @@ static bool construct(
dm_error(
"DC: failed to create output pixel processor!\n");
}
+
+ /* check next valid pipe */
+ j++;
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -1027,9 +1034,6 @@ static bool construct(
"DC:failed to create aux engine!!\n");
goto res_create_fail;
}
-
- /* check next valid pipe */
- j++;
}
/* valid pipe num */
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -366,6 +366,7 @@ static const struct resource_caps res_ca
.num_audio = 6,
.num_stream_encoder = 6,
.num_pll = 3,
+ .num_ddc = 6,
};
static const struct resource_caps res_cap_81 = {
@@ -373,6 +374,7 @@ static const struct resource_caps res_ca
.num_audio = 7,
.num_stream_encoder = 7,
.num_pll = 3,
+ .num_ddc = 6,
};
static const struct resource_caps res_cap_83 = {
@@ -380,6 +382,7 @@ static const struct resource_caps res_ca
.num_audio = 6,
.num_stream_encoder = 6,
.num_pll = 2,
+ .num_ddc = 2,
};
static const struct dce_dmcu_registers dmcu_regs = {
@@ -935,7 +938,9 @@ static bool dce80_construct(
dm_error("DC: failed to create output pixel processor!\n");
goto res_create_fail;
}
+ }
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -1131,6 +1136,16 @@ static bool dce81_construct(
}
}
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
+ if (pool->base.engines[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error(
+ "DC:failed to create aux engine!!\n");
+ goto res_create_fail;
+ }
+ }
+
dc->caps.max_planes = pool->base.pipe_count;
dc->caps.disable_dp_clk_share = true;
@@ -1312,6 +1327,16 @@ static bool dce83_construct(
goto res_create_fail;
}
}
+
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
+ if (pool->base.engines[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error(
+ "DC:failed to create aux engine!!\n");
+ goto res_create_fail;
+ }
+ }
dc->caps.max_planes = pool->base.pipe_count;
dc->caps.disable_dp_clk_share = true;
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -500,6 +500,7 @@ static const struct resource_caps res_ca
.num_audio = 4,
.num_stream_encoder = 4,
.num_pll = 4,
+ .num_ddc = 4,
};
static const struct dc_debug_options debug_defaults_drv = {
@@ -1292,7 +1293,11 @@ static bool construct(
dm_error("DC: failed to create tg!\n");
goto fail;
}
+ /* check next valid pipe */
+ j++;
+ }
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -1300,9 +1305,6 @@ static bool construct(
"DC:failed to create aux engine!!\n");
goto fail;
}
-
- /* check next valid pipe */
- j++;
}
/* valid pipe num */
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -44,6 +44,7 @@ struct resource_caps {
int num_stream_encoder;
int num_pll;
int num_dwb;
+ int num_ddc;
};
struct resource_straps {