From: Ido Schimmel <idosch@mellanox.com>
Date: Thu, 11 Oct 2018 07:48:06 +0000
Subject: mlxsw: reg: Add Tunneling NVE QoS Default Register
Patch-mainline: v4.20-rc1
Git-commit: 8efcf6bb48e52c7ee679e7f441d52dfc5dd3dc16
References: bsc#1112374
The TNQDR register configures the default QoS settings for NVE
encapsulation.
It will be used to set the default DSCP of each port to 0, so that when
DSCP is set to inherit and the overlay packet does not have an IP header
the outer DSCP will be set to 0, in accordance with the software data
path.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Reviewed-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
---
drivers/net/ethernet/mellanox/mlxsw/reg.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
@@ -8591,6 +8591,35 @@ static inline void mlxsw_reg_tnqcr_pack(
mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
}
+/* TNQDR - Tunneling NVE QoS Default Register
+ * ------------------------------------------
+ * The TNQDR register configures the default QoS settings for NVE
+ * encapsulation.
+ */
+#define MLXSW_REG_TNQDR_ID 0xA011
+#define MLXSW_REG_TNQDR_LEN 0x08
+
+MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
+
+/* reg_tnqdr_local_port
+ * Local port number (receive port). CPU port is supported.
+ * Access: Index
+ */
+MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8);
+
+/* reg_tnqdr_dscp
+ * For encapsulation, the default DSCP.
+ * Access: RW
+ */
+MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
+
+static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port)
+{
+ MLXSW_REG_ZERO(tnqdr, payload);
+ mlxsw_reg_tnqdr_local_port_set(payload, local_port);
+ mlxsw_reg_tnqdr_dscp_set(payload, 0);
+}
+
/* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register
* --------------------------------------------------------
* The TNEEM register maps ECN of the IP header at the ingress to the
@@ -9274,6 +9303,7 @@ static const struct mlxsw_reg_info *mlxs
MLXSW_REG(tngcr),
MLXSW_REG(tnumt),
MLXSW_REG(tnqcr),
+ MLXSW_REG(tnqdr),
MLXSW_REG(tneem),
MLXSW_REG(tndem),
MLXSW_REG(tnpc),