From 99b91bda84060bac061d1649fad0e3bddcf67ce6 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Thu, 1 Feb 2018 13:03:43 +0200
Subject: [PATCH] drm/i915/dp: limit DP link rate based on VBT on CNL+
Mime-version: 1.0
Content-type: text/plain; charset=UTF-8
Content-transfer-encoding: 8bit
Git-commit: 99b91bda84060bac061d1649fad0e3bddcf67ce6
Patch-mainline: v4.17-rc1
References: FATE#322643 bsc#1055900
We have the max DP link rate info available in VBT since BDB version
216, included in child device config since commit c4fb60b9aba9
("drm/i915/bios: add DP max link rate to VBT child device
struct"). Parse it and use it.
Cc: Ville Syrj채l채 <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Ville Syrj채l채 <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/a8b1364d1f2394fba3062b6ad11b474744ea4366.1517482774.git.jani.nikula@intel.com
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 21 +++++++++++++++++++++
drivers/gpu/drm/i915/intel_dp.c | 9 ++++++++-
drivers/gpu/drm/i915/intel_vbt_defs.h | 5 +++++
4 files changed, 35 insertions(+), 1 deletion(-)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1276,6 +1276,7 @@ struct ddi_vbt_port_info {
uint8_t dp_boost_level;
uint8_t hdmi_boost_level;
+ int dp_max_link_rate; /* 0 for not limited by VBT */
};
enum psr_lines_to_wait {
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1349,6 +1349,27 @@ static void parse_ddi_port(struct drm_i9
DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n",
port_name(port), info->hdmi_boost_level);
}
+
+ /* DP max link rate for CNL+ */
+ if (bdb_version >= 216) {
+ switch (child->dp_max_link_rate) {
+ default:
+ case VBT_DP_MAX_LINK_RATE_HBR3:
+ info->dp_max_link_rate = 810000;
+ break;
+ case VBT_DP_MAX_LINK_RATE_HBR2:
+ info->dp_max_link_rate = 540000;
+ break;
+ case VBT_DP_MAX_LINK_RATE_HBR:
+ info->dp_max_link_rate = 270000;
+ break;
+ case VBT_DP_MAX_LINK_RATE_LBR:
+ info->dp_max_link_rate = 162000;
+ break;
+ }
+ DRM_DEBUG_KMS("VBT DP max link rate for port %c: %d\n",
+ port_name(port), info->dp_max_link_rate);
+ }
}
static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -268,8 +268,10 @@ intel_dp_set_source_rates(struct intel_d
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ const struct ddi_vbt_port_info *info =
+ &dev_priv->vbt.ddi_port_info[dig_port->base.port];
const int *source_rates;
- int size, max_rate = 0;
+ int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
/* This should only be done once */
WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
@@ -293,6 +295,11 @@ intel_dp_set_source_rates(struct intel_d
size = ARRAY_SIZE(default_rates) - 1;
}
+ if (max_rate && vbt_max_rate)
+ max_rate = min(max_rate, vbt_max_rate);
+ else if (vbt_max_rate)
+ max_rate = vbt_max_rate;
+
if (max_rate)
size = intel_dp_rate_limit_len(source_rates, size, max_rate);
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -320,6 +320,11 @@ enum vbt_gmbus_ddi {
DDC_BUS_DDI_F,
};
+#define VBT_DP_MAX_LINK_RATE_HBR3 0
+#define VBT_DP_MAX_LINK_RATE_HBR2 1
+#define VBT_DP_MAX_LINK_RATE_HBR 2
+#define VBT_DP_MAX_LINK_RATE_LBR 3
+
/*
* The child device config, aka the display device data structure, provides a
* description of a port and its configuration on the platform.