From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Mon, 28 Aug 2017 18:53:01 +0800
Subject: PCI: artpec6: Stop enabling writes to DBI read-only registers
Git-commit: b015b37e6693de515982452eebd6a9d19201f0fe
Patch-mainline: v4.14-rc1
References: fate#326536, fate#326532
Previously we enabled writes to the DBI read-only registers so the Class
Code fix in dw_pcie_setup_rc() would work. But now dw_pcie_setup_rc()
enables write permission itself, so we don't need to do it here.
Stop enabling writes to the DBI read-only registers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
---
drivers/pci/dwc/pcie-artpec6.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index 5d81f1d884e3..d153491f600f 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -141,12 +141,6 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
usleep_range(100, 200);
- /*
- * Enable writing to config regs. This is required as the Synopsys
- * driver changes the class code. That register needs DBI write enable.
- */
- dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
-
/* setup root complex */
dw_pcie_setup_rc(pp);
--
2.11.0