From: Hersen Wu <hersenxs.wu@amd.com>
Date: Wed, 4 Jan 2017 10:22:35 -0500
Subject: drm/amd/display: Fix DP PHY test pre-emphasis not set properly
Git-commit: bf5cda339d3609408624afcb6f533f4eabc7d142
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c              |   15 +++++++++++----
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c    |    9 +++++----
 drivers/gpu/drm/amd/display/dc/dc.h                   |    3 ++-
 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c |    2 +-
 4 files changed, 19 insertions(+), 10 deletions(-)

--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -332,14 +332,21 @@ static bool setup_psr(struct dc *dc, con
 }
 
 static void set_drive_settings(struct dc *dc,
-		struct link_training_settings *lt_settings)
+		struct link_training_settings *lt_settings,
+		const struct dc_link *link)
 {
 	struct core_dc *core_dc = DC_TO_CORE(dc);
 	int i;
 
-	for (i = 0; i < core_dc->link_count; i++)
-		dc_link_dp_set_drive_settings(&core_dc->links[i]->public,
-				lt_settings);
+	for (i = 0; i < core_dc->link_count; i++) {
+		if (&core_dc->links[i]->public == link)
+			break;
+	}
+
+	if (i >= core_dc->link_count)
+		ASSERT_CRITICAL(false);
+
+	dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings);
 }
 
 static void perform_link_training(struct dc *dc,
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -229,10 +229,9 @@ void dp_retrain_link_dp_test(struct core
 					link->link_enc,
 					SIGNAL_TYPE_DISPLAY_PORT);
 
-			/* Clear current link setting.
-			 * memset(&link->public.cur_link_settings, 0,
-			 * 	sizeof(link->public.cur_link_settings));
-			 */
+			/* Clear current link setting. */
+			memset(&link->public.cur_link_settings, 0,
+				sizeof(link->public.cur_link_settings));
 
 			link->link_enc->funcs->enable_dp_output(
 						link->link_enc,
@@ -246,6 +245,8 @@ void dp_retrain_link_dp_test(struct core
 					link_setting,
 					skip_video_pattern);
 
+			link->public.cur_link_settings = *link_setting;
+
 			link->dc->hwss.unblank_stream(&pipes[i],
 					link_setting);
 		}
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -112,7 +112,8 @@ struct link_training_settings;
 
 struct dc_link_funcs {
 	void (*set_drive_settings)(struct dc *dc,
-			struct link_training_settings *lt_settings);
+			struct link_training_settings *lt_settings,
+			const struct dc_link *link);
 	void (*perform_link_training)(struct dc *dc,
 			struct dc_link_settings *link_setting,
 			bool skip_video_pattern);
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -1363,7 +1363,7 @@ void dce110_link_encoder_dp_set_lane_set
 	cntl.pixel_clock = link_settings->link_settings.link_rate *
 						LINK_RATE_REF_FREQ_IN_KHZ;
 
-	for (lane = 0; lane < link_settings->link_settings.lane_count; ++lane) {
+	for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
 		/* translate lane settings */
 
 		training_lane_set.bits.VOLTAGE_SWING_SET =