From: Tom St Denis <tom.stdenis@amd.com>
Date: Tue, 16 May 2017 10:22:03 -0400
Subject: drm/amd/display: Clean up indentation in dce120_tg_set_blank()
Git-commit: cedaf3073a33a95e276371783b20a14e208e184c
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 16 +++-------
1 file changed, 5 insertions(+), 11 deletions(-)
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -768,17 +768,11 @@ void dce120_tg_set_blank(struct timing_g
CRTC0_CRTC_DOUBLE_BUFFER_CONTROL,
CRTC_BLANK_DATA_DOUBLE_BUFFER_EN, 0);
- if (enable_blanking) {
- CRTC_REG_SET(
- CRTC0_CRTC_BLANK_CONTROL,
- CRTC_BLANK_DATA_EN, 1);
-
- } else
- dm_write_reg_soc15(
- tg->ctx,
- mmCRTC0_CRTC_BLANK_CONTROL,
- tg110->offsets.crtc,
- 0);
+ if (enable_blanking)
+ CRTC_REG_SET(CRTC0_CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
+ else
+ dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_BLANK_CONTROL,
+ tg110->offsets.crtc, 0);
}
bool dce120_tg_validate_timing(struct timing_generator *tg,