From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Date: Fri, 16 Jun 2017 11:27:59 -0400
Subject: drm/amd/display: add pipe split disable regkey
Git-commit: 90f095c13efe2aed108ebd4754dd629946b68168
Patch-mainline: v4.15-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c      |    2 +-
 drivers/gpu/drm/amd/display/dc/dc.h                   |    2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c |    4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -791,7 +791,7 @@ bool dcn_validate_bandwidth(
 	v->phyclk_per_state[1] = v->phyclkv_mid0p72;
 	v->phyclk_per_state[0] = v->phyclkv_min0p65;
 
-	if (dc->public.debug.use_max_voltage) {
+	if (dc->public.debug.disable_pipe_split) {
 		v->max_dppclk[1] = v->max_dppclk_vnom0p8;
 		v->max_dppclk[0] = v->max_dppclk_vnom0p8;
 	}
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -170,7 +170,7 @@ struct dc_debug {
 	bool disable_hubp_power_gate;
 	bool disable_pplib_wm_range;
 	bool use_dml_wm;
-	bool use_max_voltage;
+	bool disable_pipe_split;
 	int sr_exit_time_ns;
 	int sr_enter_plus_exit_time_ns;
 	int urgent_latency_ns;
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -443,7 +443,7 @@ static const struct dc_debug debug_defau
 		.disable_pplib_wm_range = false,
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 		.use_dml_wm = false,
-		.use_max_voltage = false
+		.disable_pipe_split = false
 #endif
 };
 
@@ -456,7 +456,7 @@ static const struct dc_debug debug_defau
 		.disable_pplib_clock_request = true,
 		.disable_pplib_wm_range = true,
 		.use_dml_wm = false,
-		.use_max_voltage = false
+		.disable_pipe_split = false
 #endif
 };