From: Alex Deucher <alexander.deucher@amd.com>
Date: Fri, 8 Dec 2017 11:39:49 -0500
Subject: drm/amdgpu: make function names consistent in nbio files
MIME-Version: 1.0
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Git-commit: 74e1d67c73b93634ce2436c10688a7cfea68678e
Patch-mainline: v4.16-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
All functions should have nbio_v* prefix.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 16 ++++++++--------
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 16 ++++++++--------
2 files changed, 16 insertions(+), 16 deletions(-)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -212,22 +212,22 @@ void nbio_v6_1_get_clockgating_state(str
*flags |= AMD_CG_SUPPORT_BIF_LS;
}
-static u32 get_hdp_flush_req_offset(struct amdgpu_device *adev)
+static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
}
-static u32 get_hdp_flush_done_offset(struct amdgpu_device *adev)
+static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
}
-static u32 get_pcie_index_offset(struct amdgpu_device *adev)
+static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX);
}
-static u32 get_pcie_data_offset(struct amdgpu_device *adev)
+static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA);
}
@@ -248,10 +248,10 @@ const struct nbio_hdp_flush_reg nbio_v6_
};
const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
- .get_hdp_flush_req_offset = get_hdp_flush_req_offset,
- .get_hdp_flush_done_offset = get_hdp_flush_done_offset,
- .get_pcie_index_offset = get_pcie_index_offset,
- .get_pcie_data_offset = get_pcie_data_offset,
+ .get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
+ .get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
+ .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
+ .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,
};
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -182,22 +182,22 @@ void nbio_v7_0_ih_control(struct amdgpu_
WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
}
-static u32 get_hdp_flush_req_offset(struct amdgpu_device *adev)
+static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
}
-static u32 get_hdp_flush_done_offset(struct amdgpu_device *adev)
+static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
}
-static u32 get_pcie_index_offset(struct amdgpu_device *adev)
+static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
}
-static u32 get_pcie_data_offset(struct amdgpu_device *adev)
+static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
}
@@ -218,9 +218,9 @@ const struct nbio_hdp_flush_reg nbio_v7_
};
const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
- .get_hdp_flush_req_offset = get_hdp_flush_req_offset,
- .get_hdp_flush_done_offset = get_hdp_flush_done_offset,
- .get_pcie_index_offset = get_pcie_index_offset,
- .get_pcie_data_offset = get_pcie_data_offset,
+ .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
+ .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
+ .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
+ .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset,
};