From: Rex Zhu <Rex.Zhu@amd.com>
Date: Thu, 4 Jan 2018 16:42:06 +0800
Subject: drm/amd/pp: Add a new pp feature mask bit for OD feature
Git-commit: 11f64ff5f323d697d0e3be932aaaaa5b38b144cd
Patch-mainline: v4.17-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166

when this bit was set on module load,
driver will allow the user over/under gpu
clock and voltage through sysfs.

by default, this bit was not set.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c            |    2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c        |    3 +++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   |    6 ++----
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |    7 ++-----
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |    2 ++
 5 files changed, 10 insertions(+), 10 deletions(-)

--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -120,7 +120,7 @@ uint amdgpu_pg_mask = 0xffffffff;
 uint amdgpu_sdma_phase_quantum = 32;
 char *amdgpu_disable_cu = NULL;
 char *amdgpu_virtual_display = NULL;
-uint amdgpu_pp_feature_mask = 0xffffffff;
+uint amdgpu_pp_feature_mask = 0x3fff;
 int amdgpu_ngg = 0;
 int amdgpu_prim_buf_per_se = 0;
 int amdgpu_pos_buf_per_se = 0;
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -935,6 +935,9 @@ int hwmgr_set_user_specify_caps(struct p
 			PHM_PlatformCaps_CAC);
 	}
 
+	if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)
+		hwmgr->od_enabled = true;
+
 	return 0;
 }
 
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3575,8 +3575,7 @@ static int smu7_populate_and_upload_sclk
 		dpm_table->sclk_table.dpm_levels
 		[dpm_table->sclk_table.count - 1].value = sclk;
 
-		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
-		    phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
+		if (hwmgr->od_enabled) {
 		/* Need to do calculation based on the golden DPM table
 		 * as the Heatmap GPU Clock axis is also based on the default values
 		 */
@@ -3621,8 +3620,7 @@ static int smu7_populate_and_upload_sclk
 		dpm_table->mclk_table.dpm_levels
 			[dpm_table->mclk_table.count - 1].value = mclk;
 
-		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
-		    phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
+		if (hwmgr->od_enabled) {
 
 			PP_ASSERT_WITH_CODE(
 					(golden_dpm_table->mclk_table.dpm_levels
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3399,8 +3399,7 @@ static int vega10_populate_and_upload_sc
 				dpm_table->
 				gfx_table.dpm_levels[dpm_table->gfx_table.count - 1].
 				value = sclk;
-				if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
-				    PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
+				if (hwmgr->od_enabled) {
 					/* Need to do calculation based on the golden DPM table
 					 * as the Heatmap GPU Clock axis is also based on
 					 * the default values
@@ -3454,9 +3453,7 @@ static int vega10_populate_and_upload_sc
 			mem_table.dpm_levels[dpm_table->mem_table.count - 1].
 			value = mclk;
 
-			if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
-			    PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
-
+			if (hwmgr->od_enabled) {
 				PP_ASSERT_WITH_CODE(
 					golden_dpm_table->mem_table.dpm_levels
 					[golden_dpm_table->mem_table.count - 1].value,
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -84,6 +84,7 @@ enum PP_FEATURE_MASK {
 	PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
 	PP_SOCCLK_DPM_MASK = 0x1000,
 	PP_DCEFCLK_DPM_MASK = 0x2000,
+	PP_OVERDRIVE_MASK = 0x4000,
 };
 
 enum PHM_BackEnd_Magic {
@@ -755,6 +756,7 @@ struct pp_hwmgr {
 	uint32_t power_profile_mode;
 	uint32_t pstate_sclk;
 	uint32_t pstate_mclk;
+	bool od_enabled;
 };
 
 struct cgs_irq_src_funcs {