From: Jordan Crouse <jcrouse@codeaurora.org>
Date: Thu, 26 Jul 2018 14:30:14 -0600
Subject: drm/msm/disp/dpu: Mark a handful of functions as static
Git-commit: fba33cae6aa3eaa3627a603d62d4652f12308b8d
Patch-mainline: v4.19-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
Mark a number of static functions that are only unsed in the file
that defines them and remove the prototypes from the headers where
needed.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 7 +++++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 14 --------------
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 17 -----------------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 2 +-
11 files changed, 13 insertions(+), 47 deletions(-)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -264,6 +264,9 @@ void dpu_encoder_helper_report_irq_timeo
DPU_ENCODER_FRAME_EVENT_ERROR);
}
+static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
+ int32_t hw_id, struct dpu_encoder_wait_info *info);
+
int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
enum dpu_intr_idx intr_idx,
struct dpu_encoder_wait_info *wait_info)
@@ -467,7 +470,7 @@ void dpu_encoder_get_hw_resources(struct
}
}
-void dpu_encoder_destroy(struct drm_encoder *drm_enc)
+static void dpu_encoder_destroy(struct drm_encoder *drm_enc)
{
struct dpu_encoder_virt *dpu_enc = NULL;
int i = 0;
@@ -1516,7 +1519,7 @@ void dpu_encoder_helper_trigger_start(st
}
}
-int dpu_encoder_helper_wait_event_timeout(
+static int dpu_encoder_helper_wait_event_timeout(
int32_t drm_id,
int32_t hw_id,
struct dpu_encoder_wait_info *info)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -159,12 +159,6 @@ int dpu_encoder_setup(struct drm_device
struct msm_display_info *disp_info);
/**
- * dpu_encoder_destroy - destroy previously initialized virtual encoder
- * @drm_enc: Pointer to previously created drm encoder structure
- */
-void dpu_encoder_destroy(struct drm_encoder *drm_enc);
-
-/**
* dpu_encoder_prepare_commit - prepare encoder at the very beginning of an
* atomic commit, before any registers are written
* @drm_enc: Pointer to previously created drm encoder structure
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -356,20 +356,6 @@ struct dpu_encoder_phys *dpu_encoder_phy
void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc);
/**
- * dpu_encoder_helper_wait_event_timeout - wait for event with timeout
- * taking into account that jiffies may jump between reads leading to
- * incorrectly detected timeouts. Prevent failure in this scenario by
- * making sure that elapsed time during wait is valid.
- * @drm_id: drm object id for logging
- * @hw_id: hw instance id for logging
- * @info: wait info structure
- */
-int dpu_encoder_helper_wait_event_timeout(
- int32_t drm_id,
- int32_t hw_id,
- struct dpu_encoder_wait_info *info);
-
-/**
* dpu_encoder_helper_hw_reset - issue ctl hw reset
* This helper function may be optionally specified by physical
* encoders if they require ctl hw reset. If state is currently
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -349,7 +349,7 @@ end:
return ret;
}
-void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc,
+static void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc,
bool enable)
{
struct dpu_encoder_phys_cmd *cmd_enc;
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -846,7 +846,7 @@ static int _dpu_format_get_plane_sizes_l
return 0;
}
-int dpu_format_get_plane_sizes(
+static int dpu_format_get_plane_sizes(
const struct dpu_format *fmt,
const uint32_t w,
const uint32_t h,
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
@@ -55,23 +55,6 @@ uint32_t dpu_populate_formats(
uint32_t pixel_formats_max);
/**
- * dpu_format_get_plane_sizes - calculate size and layout of given buffer format
- * @fmt: pointer to dpu_format
- * @w: width of the buffer
- * @h: height of the buffer
- * @layout: layout of the buffer
- * @pitches: array of size [DPU_MAX_PLANES] to populate
- * pitch for each plane
- *
- * Return: size of the buffer
- */
-int dpu_format_get_plane_sizes(
- const struct dpu_format *fmt,
- const uint32_t w,
- const uint32_t h,
- struct dpu_hw_fmt_layout *layout,
- const uint32_t *pitches);
-
* dpu_format_check_modified_format - validate format and buffers for
* dpu non-standard, i.e. modified format
* @kms: kms driver
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -449,7 +449,7 @@ static struct dpu_perf_cfg sdm845_perf_d
* sdm845_cfg_init(): populate sdm845 dpu sub-blocks reg offsets
* and instance counts.
*/
-void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
+static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
{
*dpu_cfg = (struct dpu_mdss_cfg){
.caps = &sdm845_dpu_caps,
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
@@ -217,7 +217,7 @@ static int dpu_hw_cdm_setup_cdwn(struct
return 0;
}
-int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx,
+static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx,
struct dpu_hw_cdm_cfg *cdm)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
@@ -249,7 +249,7 @@ int dpu_hw_cdm_enable(struct dpu_hw_cdm
return 0;
}
-void dpu_hw_cdm_disable(struct dpu_hw_cdm *ctx)
+static void dpu_hw_cdm_disable(struct dpu_hw_cdm *ctx)
{
struct cdm_output_cfg cdm_cfg = { 0 };
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -275,7 +275,7 @@ static void dpu_hw_get_safe_status(struc
status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1;
}
-void dpu_hw_reset_ubwc(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m)
+static void dpu_hw_reset_ubwc(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m)
{
struct dpu_hw_blk_reg_map c;
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -819,7 +819,7 @@ static int dpu_kms_pm_resume(struct devi
return 0;
}
-void _dpu_kms_set_encoder_mode(struct msm_kms *kms,
+static void _dpu_kms_set_encoder_mode(struct msm_kms *kms,
struct drm_encoder *encoder,
bool cmd_mode)
{
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -115,7 +115,7 @@ static int _dpu_mdss_irq_domain_add(stru
return 0;
}
-int _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss)
+static int _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss)
{
if (dpu_mdss->irq_controller.domain) {
irq_domain_remove(dpu_mdss->irq_controller.domain);