From 3b1b1ce3596458de0d5c28309954886a9cb6d5cc Mon Sep 17 00:00:00 2001
From: Alexey Kardashevskiy <aik@ozlabs.ru>
Date: Thu, 6 Jun 2019 13:25:57 +1000
Subject: [PATCH] PCI: Correct pci=resource_alignment parameter example
Git-commit: 3b1b1ce3596458de0d5c28309954886a9cb6d5cc
Patch-mainline: v5.4-rc1
References: bsc#1051510
The "pci=resource_alignment" parameter is described as requiring an order
(not a size) and the code in pci_specified_resource_alignment() expects an
order.
But the example wrongly shows a size. Convert the example to an order.
Fixes: 8b078c603249 ("PCI: Update "pci=resource_alignment" documentation")
Link: https://lore.kernel.org/r/20190606032557.107542-1-aik@ozlabs.ru
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Takashi Iwai <tiwai@suse.de>
---
Documentation/admin-guide/kernel-parameters.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -3177,12 +3177,13 @@
aligned memory resources.
If <order of align> is not specified,
PAGE_SIZE is used as alignment.
- PCI-PCI bridge can be specified, if resource
+ A PCI-PCI bridge can be specified if resource
windows need to be expanded.
To specify the alignment for several
instances of a device, the PCI vendor,
device, subvendor, and subdevice may be
- specified, e.g., 4096@pci:8086:9c22:103c:198f
+ specified, e.g., 12@pci:8086:9c22:103c:198f
+ for 4096-byte alignment.
ecrc= Enable/disable PCIe ECRC (transaction layer
end-to-end CRC checking).
bios: Use BIOS/firmware settings. This is the