From fc77426a8d69d6a706378a53b18c882578af44e5 Mon Sep 17 00:00:00 2001
From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Date: Tue, 10 Oct 2017 22:30:09 +0100
Subject: [PATCH] drm/i915: Create generic functions to control RC6, RPS
Git-commit: fc77426a8d69d6a706378a53b18c882578af44e5
Patch-mainline: v4.15-rc1
References: FATE#322643 bsc#1055900
Prepared generic functions intel_enable_rc6, intel_disable_rc6,
intel_enable_rps and intel_disable_rps functions to setup RC6/RPS
based on platforms.
V2: Make intel_enable/disable_rc6/rps static. (Chris)
V3: Added lockdep_assert_held(dev_priv->pcu_lock) in new generic
functions. (Chris)
Removed WARN_ON(&dev_priv->pcu_lock) from lower level functions as generic
function now has lockdep_assert. Rebase.
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-12-git-send-email-sagar.a.kamble@intel.com
Acked-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010213010.7415-11-chris@chris-wilson.co.uk
Acked-by: Takashi Iwai <tiwai@suse.de>
---
drivers/gpu/drm/i915/intel_pm.c | 116 ++++++++++++++++++++++++----------------
1 file changed, 70 insertions(+), 46 deletions(-)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6722,8 +6722,6 @@ static void gen6_enable_rc6(struct drm_i
int rc6_mode;
int ret;
- WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
-
I915_WRITE(GEN6_RC_STATE, 0);
/* Clear the DBG now so we don't confuse earlier errors */
@@ -6796,8 +6794,6 @@ static void gen6_enable_rc6(struct drm_i
static void gen6_enable_rps(struct drm_i915_private *dev_priv)
{
- WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
-
/* Here begins a magic sequence of register writes to enable
* auto-downclocking.
*
@@ -7218,8 +7214,6 @@ static void cherryview_enable_rc6(struct
enum intel_engine_id id;
u32 gtfifodbg, rc6_mode = 0, pcbr;
- WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
-
gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
GT_FIFO_FREE_ENTRIES_CHV);
if (gtfifodbg) {
@@ -7272,8 +7266,6 @@ static void cherryview_enable_rps(struct
{
u32 val;
- WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
-
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
/* 1: Program defaults and thresholds for RPS*/
@@ -7318,8 +7310,6 @@ static void valleyview_enable_rc6(struct
enum intel_engine_id id;
u32 gtfifodbg, rc6_mode = 0;
- WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
-
valleyview_check_pctx(dev_priv);
gtfifodbg = I915_READ(GTFIFODBG);
@@ -7365,8 +7355,6 @@ static void valleyview_enable_rps(struct
{
u32 val;
- WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
-
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
@@ -7980,31 +7968,47 @@ static inline void intel_disable_llc_pst
/* Currently there is no HW configuration to be done to disable. */
}
-void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
+static void intel_disable_rc6(struct drm_i915_private *dev_priv)
{
- struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ lockdep_assert_held(&dev_priv->pcu_lock);
- if (!READ_ONCE(rps->enabled))
- return;
+ if (INTEL_GEN(dev_priv) >= 9)
+ gen9_disable_rc6(dev_priv);
+ else if (IS_CHERRYVIEW(dev_priv))
+ cherryview_disable_rc6(dev_priv);
+ else if (IS_VALLEYVIEW(dev_priv))
+ valleyview_disable_rc6(dev_priv);
+ else if (INTEL_GEN(dev_priv) >= 6)
+ gen6_disable_rc6(dev_priv);
+}
- mutex_lock(&dev_priv->pcu_lock);
+static void intel_disable_rps(struct drm_i915_private *dev_priv)
+{
+ lockdep_assert_held(&dev_priv->pcu_lock);
- if (INTEL_GEN(dev_priv) >= 9) {
- gen9_disable_rc6(dev_priv);
+ if (INTEL_GEN(dev_priv) >= 9)
gen9_disable_rps(dev_priv);
- } else if (IS_CHERRYVIEW(dev_priv)) {
- cherryview_disable_rc6(dev_priv);
+ else if (IS_CHERRYVIEW(dev_priv))
cherryview_disable_rps(dev_priv);
- } else if (IS_VALLEYVIEW(dev_priv)) {
- valleyview_disable_rc6(dev_priv);
+ else if (IS_VALLEYVIEW(dev_priv))
valleyview_disable_rps(dev_priv);
- } else if (INTEL_GEN(dev_priv) >= 6) {
- gen6_disable_rc6(dev_priv);
+ else if (INTEL_GEN(dev_priv) >= 6)
gen6_disable_rps(dev_priv);
- } else if (IS_IRONLAKE_M(dev_priv)) {
+ else if (IS_IRONLAKE_M(dev_priv))
ironlake_disable_drps(dev_priv);
- }
+}
+void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
+{
+ struct intel_rps *rps = &dev_priv->gt_pm.rps;
+
+ if (!READ_ONCE(rps->enabled))
+ return;
+
+ mutex_lock(&dev_priv->pcu_lock);
+
+ intel_disable_rc6(dev_priv);
+ intel_disable_rps(dev_priv);
if (HAS_LLC(dev_priv))
intel_disable_llc_pstate(dev_priv);
@@ -8019,50 +8023,70 @@ static inline void intel_enable_llc_psta
gen6_update_ring_freq(i915);
}
-void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
+static void intel_enable_rc6(struct drm_i915_private *dev_priv)
{
- struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ lockdep_assert_held(&dev_priv->pcu_lock);
- /* We shouldn't be disabling as we submit, so this should be less
- * racy than it appears!
- */
- if (READ_ONCE(rps->enabled))
- return;
+ if (IS_CHERRYVIEW(dev_priv))
+ cherryview_enable_rc6(dev_priv);
+ else if (IS_VALLEYVIEW(dev_priv))
+ valleyview_enable_rc6(dev_priv);
+ else if (INTEL_GEN(dev_priv) >= 9)
+ gen9_enable_rc6(dev_priv);
+ else if (IS_BROADWELL(dev_priv))
+ gen8_enable_rc6(dev_priv);
+ else if (INTEL_GEN(dev_priv) >= 6)
+ gen6_enable_rc6(dev_priv);
+}
- /* Powersaving is controlled by the host when inside a VM */
- if (intel_vgpu_active(dev_priv))
- return;
+static void intel_enable_rps(struct drm_i915_private *dev_priv)
+{
+ struct intel_rps *rps = &dev_priv->gt_pm.rps;
- mutex_lock(&dev_priv->pcu_lock);
+ lockdep_assert_held(&dev_priv->pcu_lock);
if (IS_CHERRYVIEW(dev_priv)) {
- cherryview_enable_rc6(dev_priv);
cherryview_enable_rps(dev_priv);
} else if (IS_VALLEYVIEW(dev_priv)) {
- valleyview_enable_rc6(dev_priv);
valleyview_enable_rps(dev_priv);
} else if (INTEL_GEN(dev_priv) >= 9) {
- gen9_enable_rc6(dev_priv);
gen9_enable_rps(dev_priv);
} else if (IS_BROADWELL(dev_priv)) {
- gen8_enable_rc6(dev_priv);
gen8_enable_rps(dev_priv);
} else if (INTEL_GEN(dev_priv) >= 6) {
- gen6_enable_rc6(dev_priv);
gen6_enable_rps(dev_priv);
} else if (IS_IRONLAKE_M(dev_priv)) {
ironlake_enable_drps(dev_priv);
intel_init_emon(dev_priv);
}
- if (HAS_LLC(dev_priv))
- intel_enable_llc_pstate(dev_priv);
-
WARN_ON(rps->max_freq < rps->min_freq);
WARN_ON(rps->idle_freq > rps->max_freq);
WARN_ON(rps->efficient_freq < rps->min_freq);
WARN_ON(rps->efficient_freq > rps->max_freq);
+}
+
+void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
+{
+ struct intel_rps *rps = &dev_priv->gt_pm.rps;
+
+ /* We shouldn't be disabling as we submit, so this should be less
+ * racy than it appears!
+ */
+ if (READ_ONCE(rps->enabled))
+ return;
+
+ /* Powersaving is controlled by the host when inside a VM */
+ if (intel_vgpu_active(dev_priv))
+ return;
+
+ mutex_lock(&dev_priv->pcu_lock);
+
+ intel_enable_rc6(dev_priv);
+ intel_enable_rps(dev_priv);
+ if (HAS_LLC(dev_priv))
+ intel_enable_llc_pstate(dev_priv);
rps->enabled = true;
mutex_unlock(&dev_priv->pcu_lock);