From ef266f5a04461d5706aca0ec461b6dc96a6c574e Mon Sep 17 00:00:00 2001
From: Eric Bernstein <eric.bernstein@amd.com>
Date: Mon, 30 Jul 2018 17:43:23 -0400
Subject: drm/amd/display: Fix null timing generator resource
Git-commit: c1127df9515ca781940927deffc5ae657ed73a5f
Patch-mainline: v6.0-rc1
References: jsc#PED-1166 jsc#PED-1168 jsc#PED-1170 jsc#PED-1218 jsc#PED-1220 jsc#PED-1222 jsc#PED-1223 jsc#PED-1225 jsc#PED-2849
[Why]
For some customer blending transition cases, the
available pipe for second stream is a pipe index that is
greater than the number of timing generators, which
can cause a problem in acquire_first_free_pipe since it
assumes same index for pipe and timing generator
[How]
Added logic to use last timing generator index
if the pipe index is greater than number of timing generators.
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 838dd002ccd8..807419c19b1f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1886,6 +1886,12 @@ static int acquire_first_free_pipe(
pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
pipe_ctx->pipe_idx = i;
+ if (i >= pool->timing_generator_count) {
+ int tg_inst = pool->timing_generator_count - 1;
+
+ pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
+ pipe_ctx->stream_res.opp = pool->opps[tg_inst];
+ }
pipe_ctx->stream = stream;
return i;
--
2.38.1