From: Alex Deucher <alexander.deucher@amd.com>
Date: Wed, 29 Mar 2017 13:23:44 -0400
Subject: drm/amdgpu: split gfx_v8_0_kiq_init_queue into two
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Git-commit: 3930011594af82812b69551ce96aefef7c1ac1a9
Patch-mainline: v4.13-rc1
References: FATE#326289 FATE#326079 FATE#326049 FATE#322398 FATE#326166
One for KIQ and one for the KCQ. This simplifies the logic and
allows for future optimizations.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Petr Tesarik <ptesarik@suse.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 62 ++++++++++++++++++++++------------
1 file changed, 41 insertions(+), 21 deletions(-)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4899,25 +4899,18 @@ static int gfx_v8_0_kiq_init_register(st
static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_kiq *kiq = &adev->gfx.kiq;
struct vi_mqd *mqd = ring->mqd_ptr;
- bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ);
int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
int r;
- if (is_kiq) {
- gfx_v8_0_kiq_setting(&kiq->ring);
- } else {
- mqd_idx = ring - &adev->gfx.compute_ring[0];
- }
+ gfx_v8_0_kiq_setting(ring);
if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
memset((void *)mqd, 0, sizeof(*mqd));
mutex_lock(&adev->srbm_mutex);
vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
gfx_v8_0_mqd_init(ring);
- if (is_kiq)
- gfx_v8_0_kiq_init_register(ring);
+ gfx_v8_0_kiq_init_register(ring);
vi_srbm_select(adev, 0, 0, 0, 0);
mutex_unlock(&adev->srbm_mutex);
@@ -4932,19 +4925,46 @@ static int gfx_v8_0_kiq_init_queue(struc
ring->wptr = 0;
amdgpu_ring_clear_ring(ring);
- if (is_kiq) {
- mutex_lock(&adev->srbm_mutex);
- vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
- gfx_v8_0_kiq_init_register(ring);
- vi_srbm_select(adev, 0, 0, 0, 0);
- mutex_unlock(&adev->srbm_mutex);
- }
+ mutex_lock(&adev->srbm_mutex);
+ vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+ gfx_v8_0_kiq_init_register(ring);
+ vi_srbm_select(adev, 0, 0, 0, 0);
+ mutex_unlock(&adev->srbm_mutex);
+ }
+
+ r = gfx_v8_0_kiq_enable(ring);
+
+ return r;
+}
+
+static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ struct vi_mqd *mqd = ring->mqd_ptr;
+ int mqd_idx = ring - &adev->gfx.compute_ring[0];
+ int r;
+
+ if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
+ memset((void *)mqd, 0, sizeof(*mqd));
+ mutex_lock(&adev->srbm_mutex);
+ vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+ gfx_v8_0_mqd_init(ring);
+ vi_srbm_select(adev, 0, 0, 0, 0);
+ mutex_unlock(&adev->srbm_mutex);
+
+ if (adev->gfx.mec.mqd_backup[mqd_idx])
+ memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
+ } else { /* for GPU_RESET case */
+ /* reset MQD to a clean status */
+ if (adev->gfx.mec.mqd_backup[mqd_idx])
+ memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
+
+ /* reset ring buffer */
+ ring->wptr = 0;
+ amdgpu_ring_clear_ring(ring);
}
- if (is_kiq)
- r = gfx_v8_0_kiq_enable(ring);
- else
- r = gfx_v8_0_map_queue_enable(&kiq->ring, ring);
+ r = gfx_v8_0_map_queue_enable(&kiq->ring, ring);
return r;
}
@@ -4987,7 +5007,7 @@ static int gfx_v8_0_kiq_resume(struct am
goto done;
r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
if (!r) {
- r = gfx_v8_0_kiq_init_queue(ring);
+ r = gfx_v8_0_kcq_init_queue(ring);
amdgpu_bo_kunmap(ring->mqd_obj);
ring->mqd_ptr = NULL;
}