From 2319a18d7d70ec12dc3da23c2b457ca1bb472e32 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Mon, 21 Feb 2022 13:03:55 +0200
Subject: drm/i915: Relocate ibx pch port sanitation code
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Git-commit: 108a112f5ebaf9481af805a32167f8ce805e3608
Patch-mainline: v5.19-rc1
References: jsc#PED-1166 jsc#PED-1168 jsc#PED-1170 jsc#PED-1218 jsc#PED-1220 jsc#PED-1222 jsc#PED-1223 jsc#PED-1225
Move the ibx pch port sanitation code into intel_pch_display.c
where it now belongs.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220221110356.5532-3-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/i915/display/intel_display.c | 63 +----------------
.../gpu/drm/i915/display/intel_pch_display.c | 67 +++++++++++++++++++
.../gpu/drm/i915/display/intel_pch_display.h | 3 +
3 files changed, 71 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ad4a631833d8..b00084dc53cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10362,66 +10362,6 @@ static void intel_early_display_was(struct drm_i915_private *dev_priv)
}
}
-static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
- enum port port, i915_reg_t hdmi_reg)
-{
- u32 val = intel_de_read(dev_priv, hdmi_reg);
-
- if (val & SDVO_ENABLE ||
- (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
- return;
-
- drm_dbg_kms(&dev_priv->drm,
- "Sanitizing transcoder select for HDMI %c\n",
- port_name(port));
-
- val &= ~SDVO_PIPE_SEL_MASK;
- val |= SDVO_PIPE_SEL(PIPE_A);
-
- intel_de_write(dev_priv, hdmi_reg, val);
-}
-
-static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
- enum port port, i915_reg_t dp_reg)
-{
- u32 val = intel_de_read(dev_priv, dp_reg);
-
- if (val & DP_PORT_EN ||
- (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
- return;
-
- drm_dbg_kms(&dev_priv->drm,
- "Sanitizing transcoder select for DP %c\n",
- port_name(port));
-
- val &= ~DP_PIPE_SEL_MASK;
- val |= DP_PIPE_SEL(PIPE_A);
-
- intel_de_write(dev_priv, dp_reg, val);
-}
-
-static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
-{
- /*
- * The BIOS may select transcoder B on some of the PCH
- * ports even it doesn't enable the port. This would trip
- * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
- * Sanitize the transcoder select bits to prevent that. We
- * assume that the BIOS never actually enabled the port,
- * because if it did we'd actually have to toggle the port
- * on and back off to make the transcoder A select stick
- * (see. intel_dp_link_down(), intel_disable_hdmi(),
- * intel_disable_sdvo()).
- */
- ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
- ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
- ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
-
- /* PCH SDVOB multiplex with HDMIB */
- ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
- ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
- ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
-}
/* Scan out the current hw modeset state,
* and sanitizes it to the current state
@@ -10443,8 +10383,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
/* HW state is read out, now we need to sanitize this mess. */
get_encoder_power_domains(dev_priv);
- if (HAS_PCH_IBX(dev_priv))
- ibx_sanitize_pch_ports(dev_priv);
+ intel_pch_sanitize(dev_priv);
/*
* intel_sanitize_plane_mapping() may need to do vblank
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 00232dab217d..43e717f4f8e7 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -88,6 +88,67 @@ static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
pipe_name(pipe));
}
+static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
+ enum port port, i915_reg_t hdmi_reg)
+{
+ u32 val = intel_de_read(dev_priv, hdmi_reg);
+
+ if (val & SDVO_ENABLE ||
+ (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
+ return;
+
+ drm_dbg_kms(&dev_priv->drm,
+ "Sanitizing transcoder select for HDMI %c\n",
+ port_name(port));
+
+ val &= ~SDVO_PIPE_SEL_MASK;
+ val |= SDVO_PIPE_SEL(PIPE_A);
+
+ intel_de_write(dev_priv, hdmi_reg, val);
+}
+
+static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
+ enum port port, i915_reg_t dp_reg)
+{
+ u32 val = intel_de_read(dev_priv, dp_reg);
+
+ if (val & DP_PORT_EN ||
+ (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
+ return;
+
+ drm_dbg_kms(&dev_priv->drm,
+ "Sanitizing transcoder select for DP %c\n",
+ port_name(port));
+
+ val &= ~DP_PIPE_SEL_MASK;
+ val |= DP_PIPE_SEL(PIPE_A);
+
+ intel_de_write(dev_priv, dp_reg, val);
+}
+
+static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
+{
+ /*
+ * The BIOS may select transcoder B on some of the PCH
+ * ports even it doesn't enable the port. This would trip
+ * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
+ * Sanitize the transcoder select bits to prevent that. We
+ * assume that the BIOS never actually enabled the port,
+ * because if it did we'd actually have to toggle the port
+ * on and back off to make the transcoder A select stick
+ * (see. intel_dp_link_down(), intel_disable_hdmi(),
+ * intel_disable_sdvo()).
+ */
+ ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
+ ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
+ ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
+
+ /* PCH SDVOB multiplex with HDMIB */
+ ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
+ ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
+ ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
+}
+
static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,
const struct intel_link_m_n *m_n)
{
@@ -564,3 +625,9 @@ void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
}
+
+void intel_pch_sanitize(struct drm_i915_private *i915)
+{
+ if (HAS_PCH_IBX(i915))
+ ibx_sanitize_pch_ports(i915);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
index 749473d99320..4ef033bb5807 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.h
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
@@ -6,6 +6,7 @@
#ifndef _INTEL_PCH_DISPLAY_H_
#define _INTEL_PCH_DISPLAY_H_
+struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
@@ -32,4 +33,6 @@ void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
struct intel_link_m_n *m_n);
+void intel_pch_sanitize(struct drm_i915_private *i915);
+
#endif
--
2.38.1