From 5b011f1f9f1caf59892e157364eac977e1a9b7be Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Wed, 30 Mar 2022 14:34:17 +0300
Subject: drm/i915/dmc: split out dmc registers to a separate file
Git-commit: 9c67d9e84c7d4a3a2371a54ee2dddc4699002000
Patch-mainline: v5.19-rc1
References: jsc#PED-1166 jsc#PED-1168 jsc#PED-1170 jsc#PED-1218 jsc#PED-1220 jsc#PED-1222 jsc#PED-1223 jsc#PED-1225
Clean up the massive i915_reg.h a bit with this isolated set of
registers.
v2: Remove stale comment (Lucas)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220330113417.220964-3-jani.nikula@intel.com
Acked-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 1 +
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 46 +++++++++++++++++++
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 37 ---------------
4 files changed, 48 insertions(+), 37 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 6e3711ace3e5..a171d42a5c5b 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -28,6 +28,7 @@
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_dmc.h"
+#include "intel_dmc_regs.h"
/**
* DOC: DMC Firmware Support
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
new file mode 100644
index 000000000000..7853827988d4
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_DMC_REGS_H__
+#define __INTEL_DMC_REGS_H__
+
+#include "i915_reg_defs.h"
+
+#define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
+#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
+#define DMC_HTP_ADDR_SKL 0x00500034
+#define DMC_SSP_BASE _MMIO(0x8F074)
+#define DMC_HTP_SKL _MMIO(0x8F004)
+#define DMC_LAST_WRITE _MMIO(0x8F034)
+#define DMC_LAST_WRITE_VALUE 0xc003b400
+#define DMC_MMIO_START_RANGE 0x80000
+#define DMC_MMIO_END_RANGE 0x8FFFF
+#define DMC_V1_MMIO_START_RANGE 0x80000
+#define TGL_MAIN_MMIO_START 0x8F000
+#define TGL_MAIN_MMIO_END 0x8FFFF
+#define _TGL_PIPEA_MMIO_START 0x92000
+#define _TGL_PIPEA_MMIO_END 0x93FFF
+#define _TGL_PIPEB_MMIO_START 0x96000
+#define _TGL_PIPEB_MMIO_END 0x97FFF
+#define ADLP_PIPE_MMIO_START 0x5F000
+#define ADLP_PIPE_MMIO_END 0x5FFFF
+
+#define TGL_PIPE_MMIO_START(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_START,\
+ _TGL_PIPEB_MMIO_START)
+
+#define TGL_PIPE_MMIO_END(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_END,\
+ _TGL_PIPEB_MMIO_END)
+
+#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
+#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
+#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
+#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
+#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
+#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
+
+#define TGL_DMC_DEBUG3 _MMIO(0x101090)
+#define DG1_DMC_DEBUG3 _MMIO(0x13415c)
+
+#endif /* __INTEL_DMC_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 0ee3ecc83234..57b0f4977760 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -42,6 +42,7 @@
#include "i915_pvinfo.h"
#include "intel_mchbar_regs.h"
#include "display/intel_display_types.h"
+#include "display/intel_dmc_regs.h"
#include "display/intel_fbc.h"
#include "display/vlv_dsi_pll_regs.h"
#include "gt/intel_gt_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index de98d4e4baad..a5e405196c6f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5498,43 +5498,6 @@
#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
-/* DMC */
-#define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
-#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
-#define DMC_HTP_ADDR_SKL 0x00500034
-#define DMC_SSP_BASE _MMIO(0x8F074)
-#define DMC_HTP_SKL _MMIO(0x8F004)
-#define DMC_LAST_WRITE _MMIO(0x8F034)
-#define DMC_LAST_WRITE_VALUE 0xc003b400
-/* MMIO address range for DMC program (0x80000 - 0x82FFF) */
-#define DMC_MMIO_START_RANGE 0x80000
-#define DMC_MMIO_END_RANGE 0x8FFFF
-#define DMC_V1_MMIO_START_RANGE 0x80000
-#define TGL_MAIN_MMIO_START 0x8F000
-#define TGL_MAIN_MMIO_END 0x8FFFF
-#define _TGL_PIPEA_MMIO_START 0x92000
-#define _TGL_PIPEA_MMIO_END 0x93FFF
-#define _TGL_PIPEB_MMIO_START 0x96000
-#define _TGL_PIPEB_MMIO_END 0x97FFF
-#define ADLP_PIPE_MMIO_START 0x5F000
-#define ADLP_PIPE_MMIO_END 0x5FFFF
-
-#define TGL_PIPE_MMIO_START(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_START,\
- _TGL_PIPEB_MMIO_START)
-
-#define TGL_PIPE_MMIO_END(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_END,\
- _TGL_PIPEB_MMIO_END)
-
-#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
-#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
-#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
-#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
-#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
-#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
-
-#define TGL_DMC_DEBUG3 _MMIO(0x101090)
-#define DG1_DMC_DEBUG3 _MMIO(0x13415c)
-
/* Display Internal Timeout Register */
#define RM_TIMEOUT _MMIO(0x42060)
#define MMIO_TIMEOUT_US(us) ((us) << 0)
--
2.38.1