From b51441685203640139eee896b395793425e0d989 Mon Sep 17 00:00:00 2001
From: Huang Rui <ray.huang@amd.com>
Date: Thu, 12 May 2022 16:03:34 +0800
Subject: drm/amdgpu: add mmhub v3_0_1 headers
Git-commit: d57716702deac8e0ec440739eb4cd6eb0872ddd4
Patch-mainline: v6.0-rc1
References: jsc#PED-1166 jsc#PED-1168 jsc#PED-1170 jsc#PED-1218 jsc#PED-1220 jsc#PED-1222 jsc#PED-1223 jsc#PED-1225 jsc#PED-2849
Add mmhub v3_0_1 headers, because there are many differeces with v3_0_0.
v2: squash in updates (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Patrik Jakobsson <pjakobsson@suse.de>
---
.../asic_reg/mmhub/mmhub_3_0_1_offset.h | 1769 ++++
.../asic_reg/mmhub/mmhub_3_0_1_sh_mask.h | 7483 +++++++++++++++++
2 files changed, 9252 insertions(+)
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h
new file mode 100644
index 000000000000..6baac6ae2007
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h
@@ -0,0 +1,1769 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _mmhub_3_0_1_OFFSET_HEADER
+#define _mmhub_3_0_1_OFFSET_HEADER
+
+
+
+// addressBlock: mmhub_dagbdec
+// base address: 0x68000
+#define regDAGB0_RDCLI0 0x0000
+#define regDAGB0_RDCLI0_BASE_IDX 1
+#define regDAGB0_RDCLI1 0x0001
+#define regDAGB0_RDCLI1_BASE_IDX 1
+#define regDAGB0_RDCLI2 0x0002
+#define regDAGB0_RDCLI2_BASE_IDX 1
+#define regDAGB0_RDCLI3 0x0003
+#define regDAGB0_RDCLI3_BASE_IDX 1
+#define regDAGB0_RDCLI4 0x0004
+#define regDAGB0_RDCLI4_BASE_IDX 1
+#define regDAGB0_RDCLI5 0x0005
+#define regDAGB0_RDCLI5_BASE_IDX 1
+#define regDAGB0_RDCLI6 0x0006
+#define regDAGB0_RDCLI6_BASE_IDX 1
+#define regDAGB0_RDCLI7 0x0007
+#define regDAGB0_RDCLI7_BASE_IDX 1
+#define regDAGB0_RDCLI8 0x0008
+#define regDAGB0_RDCLI8_BASE_IDX 1
+#define regDAGB0_RDCLI9 0x0009
+#define regDAGB0_RDCLI9_BASE_IDX 1
+#define regDAGB0_RDCLI10 0x000a
+#define regDAGB0_RDCLI10_BASE_IDX 1
+#define regDAGB0_RDCLI11 0x000b
+#define regDAGB0_RDCLI11_BASE_IDX 1
+#define regDAGB0_RDCLI12 0x000c
+#define regDAGB0_RDCLI12_BASE_IDX 1
+#define regDAGB0_RDCLI13 0x000d
+#define regDAGB0_RDCLI13_BASE_IDX 1
+#define regDAGB0_RDCLI14 0x000e
+#define regDAGB0_RDCLI14_BASE_IDX 1
+#define regDAGB0_RDCLI15 0x000f
+#define regDAGB0_RDCLI15_BASE_IDX 1
+#define regDAGB0_RDCLI16 0x0010
+#define regDAGB0_RDCLI16_BASE_IDX 1
+#define regDAGB0_RDCLI17 0x0011
+#define regDAGB0_RDCLI17_BASE_IDX 1
+#define regDAGB0_RDCLI18 0x0012
+#define regDAGB0_RDCLI18_BASE_IDX 1
+#define regDAGB0_RDCLI19 0x0013
+#define regDAGB0_RDCLI19_BASE_IDX 1
+#define regDAGB0_RDCLI20 0x0014
+#define regDAGB0_RDCLI20_BASE_IDX 1
+#define regDAGB0_RDCLI21 0x0015
+#define regDAGB0_RDCLI21_BASE_IDX 1
+#define regDAGB0_RDCLI22 0x0016
+#define regDAGB0_RDCLI22_BASE_IDX 1
+#define regDAGB0_RDCLI23 0x0017
+#define regDAGB0_RDCLI23_BASE_IDX 1
+#define regDAGB0_RDCLI24 0x0018
+#define regDAGB0_RDCLI24_BASE_IDX 1
+#define regDAGB0_RDCLI25 0x0019
+#define regDAGB0_RDCLI25_BASE_IDX 1
+#define regDAGB0_RDCLI26 0x001a
+#define regDAGB0_RDCLI26_BASE_IDX 1
+#define regDAGB0_RDCLI27 0x001b
+#define regDAGB0_RDCLI27_BASE_IDX 1
+#define regDAGB0_RDCLI28 0x001c
+#define regDAGB0_RDCLI28_BASE_IDX 1
+#define regDAGB0_RDCLI29 0x001d
+#define regDAGB0_RDCLI29_BASE_IDX 1
+#define regDAGB0_RD_CNTL 0x001e
+#define regDAGB0_RD_CNTL_BASE_IDX 1
+#define regDAGB0_RD_IO_CNTL 0x001f
+#define regDAGB0_RD_IO_CNTL_BASE_IDX 1
+#define regDAGB0_RD_GMI_CNTL 0x0020
+#define regDAGB0_RD_GMI_CNTL_BASE_IDX 1
+#define regDAGB0_RD_ADDR_DAGB 0x0021
+#define regDAGB0_RD_ADDR_DAGB_BASE_IDX 1
+#define regDAGB0_RD_CGTT_CLK_CTRL 0x0022
+#define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 1
+#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0023
+#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0024
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0025
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x0026
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x0027
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x0028
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 1
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x0029
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST3 0x002a
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST3_BASE_IDX 1
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER3 0x002b
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 1
+#define regDAGB0_RD_VC0_CNTL 0x002c
+#define regDAGB0_RD_VC0_CNTL_BASE_IDX 1
+#define regDAGB0_RD_VC1_CNTL 0x002d
+#define regDAGB0_RD_VC1_CNTL_BASE_IDX 1
+#define regDAGB0_RD_VC2_CNTL 0x002e
+#define regDAGB0_RD_VC2_CNTL_BASE_IDX 1
+#define regDAGB0_RD_VC3_CNTL 0x002f
+#define regDAGB0_RD_VC3_CNTL_BASE_IDX 1
+#define regDAGB0_RD_VC4_CNTL 0x0030
+#define regDAGB0_RD_VC4_CNTL_BASE_IDX 1
+#define regDAGB0_RD_VC5_CNTL 0x0031
+#define regDAGB0_RD_VC5_CNTL_BASE_IDX 1
+#define regDAGB0_RD_IO_VC_CNTL 0x0032
+#define regDAGB0_RD_IO_VC_CNTL_BASE_IDX 1
+#define regDAGB0_RD_GMI_VC_CNTL 0x0033
+#define regDAGB0_RD_GMI_VC_CNTL_BASE_IDX 1
+#define regDAGB0_RD_CNTL_MISC 0x0034
+#define regDAGB0_RD_CNTL_MISC_BASE_IDX 1
+#define regDAGB0_RD_TLB_CREDIT 0x0035
+#define regDAGB0_RD_TLB_CREDIT_BASE_IDX 1
+#define regDAGB0_RDCLI_ASK_PENDING 0x0036
+#define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 1
+#define regDAGB0_RDCLI_GO_PENDING 0x0037
+#define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 1
+#define regDAGB0_RDCLI_GBLSEND_PENDING 0x0038
+#define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 1
+#define regDAGB0_RDCLI_TLB_PENDING 0x0039
+#define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 1
+#define regDAGB0_RDCLI_OARB_PENDING 0x003a
+#define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 1
+#define regDAGB0_RDCLI_ASK2ARB_PENDING 0x003b
+#define regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX 1
+#define regDAGB0_RDCLI_ASK2DF_PENDING 0x003c
+#define regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX 1
+#define regDAGB0_RDCLI_OSD_PENDING 0x003d
+#define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 1
+#define regDAGB0_RDCLI_ASK_OSD_PENDING 0x003e
+#define regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX 1
+#define regDAGB0_WRCLI0 0x003f
+#define regDAGB0_WRCLI0_BASE_IDX 1
+#define regDAGB0_WRCLI1 0x0040
+#define regDAGB0_WRCLI1_BASE_IDX 1
+#define regDAGB0_WRCLI2 0x0041
+#define regDAGB0_WRCLI2_BASE_IDX 1
+#define regDAGB0_WRCLI3 0x0042
+#define regDAGB0_WRCLI3_BASE_IDX 1
+#define regDAGB0_WRCLI4 0x0043
+#define regDAGB0_WRCLI4_BASE_IDX 1
+#define regDAGB0_WRCLI5 0x0044
+#define regDAGB0_WRCLI5_BASE_IDX 1
+#define regDAGB0_WRCLI6 0x0045
+#define regDAGB0_WRCLI6_BASE_IDX 1
+#define regDAGB0_WRCLI7 0x0046
+#define regDAGB0_WRCLI7_BASE_IDX 1
+#define regDAGB0_WRCLI8 0x0047
+#define regDAGB0_WRCLI8_BASE_IDX 1
+#define regDAGB0_WRCLI9 0x0048
+#define regDAGB0_WRCLI9_BASE_IDX 1
+#define regDAGB0_WRCLI10 0x0049
+#define regDAGB0_WRCLI10_BASE_IDX 1
+#define regDAGB0_WRCLI11 0x004a
+#define regDAGB0_WRCLI11_BASE_IDX 1
+#define regDAGB0_WRCLI12 0x004b
+#define regDAGB0_WRCLI12_BASE_IDX 1
+#define regDAGB0_WRCLI13 0x004c
+#define regDAGB0_WRCLI13_BASE_IDX 1
+#define regDAGB0_WRCLI14 0x004d
+#define regDAGB0_WRCLI14_BASE_IDX 1
+#define regDAGB0_WRCLI15 0x004e
+#define regDAGB0_WRCLI15_BASE_IDX 1
+#define regDAGB0_WRCLI16 0x004f
+#define regDAGB0_WRCLI16_BASE_IDX 1
+#define regDAGB0_WRCLI17 0x0050
+#define regDAGB0_WRCLI17_BASE_IDX 1
+#define regDAGB0_WRCLI18 0x0051
+#define regDAGB0_WRCLI18_BASE_IDX 1
+#define regDAGB0_WRCLI19 0x0052
+#define regDAGB0_WRCLI19_BASE_IDX 1
+#define regDAGB0_WRCLI20 0x0053
+#define regDAGB0_WRCLI20_BASE_IDX 1
+#define regDAGB0_WRCLI21 0x0054
+#define regDAGB0_WRCLI21_BASE_IDX 1
+#define regDAGB0_WRCLI22 0x0055
+#define regDAGB0_WRCLI22_BASE_IDX 1
+#define regDAGB0_WRCLI23 0x0056
+#define regDAGB0_WRCLI23_BASE_IDX 1
+#define regDAGB0_WRCLI24 0x0057
+#define regDAGB0_WRCLI24_BASE_IDX 1
+#define regDAGB0_WRCLI25 0x0058
+#define regDAGB0_WRCLI25_BASE_IDX 1
+#define regDAGB0_WRCLI26 0x0059
+#define regDAGB0_WRCLI26_BASE_IDX 1
+#define regDAGB0_WRCLI27 0x005a
+#define regDAGB0_WRCLI27_BASE_IDX 1
+#define regDAGB0_WRCLI28 0x005b
+#define regDAGB0_WRCLI28_BASE_IDX 1
+#define regDAGB0_WRCLI29 0x005c
+#define regDAGB0_WRCLI29_BASE_IDX 1
+#define regDAGB0_WR_CNTL 0x005d
+#define regDAGB0_WR_CNTL_BASE_IDX 1
+#define regDAGB0_WR_IO_CNTL 0x005e
+#define regDAGB0_WR_IO_CNTL_BASE_IDX 1
+#define regDAGB0_WR_GMI_CNTL 0x005f
+#define regDAGB0_WR_GMI_CNTL_BASE_IDX 1
+#define regDAGB0_WR_ADDR_DAGB 0x0060
+#define regDAGB0_WR_ADDR_DAGB_BASE_IDX 1
+#define regDAGB0_WR_CGTT_CLK_CTRL 0x0061
+#define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 1
+#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0062
+#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0063
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0064
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0065
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0066
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x0067
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 1
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x0068
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST3 0x0069
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST3_BASE_IDX 1
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER3 0x006a
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 1
+#define regDAGB0_WR_DATA_DAGB 0x006b
+#define regDAGB0_WR_DATA_DAGB_BASE_IDX 1
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x006c
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x006d
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x006e
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x006f
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0070
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 1
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0071
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 1
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST3 0x0072
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST3_BASE_IDX 1
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER3 0x0073
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER3_BASE_IDX 1
+#define regDAGB0_WR_VC0_CNTL 0x0074
+#define regDAGB0_WR_VC0_CNTL_BASE_IDX 1
+#define regDAGB0_WR_VC1_CNTL 0x0075
+#define regDAGB0_WR_VC1_CNTL_BASE_IDX 1
+#define regDAGB0_WR_VC2_CNTL 0x0076
+#define regDAGB0_WR_VC2_CNTL_BASE_IDX 1
+#define regDAGB0_WR_VC3_CNTL 0x0077
+#define regDAGB0_WR_VC3_CNTL_BASE_IDX 1
+#define regDAGB0_WR_VC4_CNTL 0x0078
+#define regDAGB0_WR_VC4_CNTL_BASE_IDX 1
+#define regDAGB0_WR_VC5_CNTL 0x0079
+#define regDAGB0_WR_VC5_CNTL_BASE_IDX 1
+#define regDAGB0_WR_IO_VC_CNTL 0x007a
+#define regDAGB0_WR_IO_VC_CNTL_BASE_IDX 1
+#define regDAGB0_WR_GMI_VC_CNTL 0x007b
+#define regDAGB0_WR_GMI_VC_CNTL_BASE_IDX 1
+#define regDAGB0_WR_CNTL_MISC 0x007c
+#define regDAGB0_WR_CNTL_MISC_BASE_IDX 1
+#define regDAGB0_WR_TLB_CREDIT 0x007d
+#define regDAGB0_WR_TLB_CREDIT_BASE_IDX 1
+#define regDAGB0_WR_DATA_CREDIT 0x007e
+#define regDAGB0_WR_DATA_CREDIT_BASE_IDX 1
+#define regDAGB0_WR_MISC_CREDIT 0x007f
+#define regDAGB0_WR_MISC_CREDIT_BASE_IDX 1
+#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 0x0080
+#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX 1
+#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x0081
+#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 1
+#define regDAGB0_WRCLI_ASK_PENDING 0x0082
+#define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 1
+#define regDAGB0_WRCLI_GO_PENDING 0x0083
+#define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 1
+#define regDAGB0_WRCLI_GBLSEND_PENDING 0x0084
+#define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 1
+#define regDAGB0_WRCLI_TLB_PENDING 0x0085
+#define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 1
+#define regDAGB0_WRCLI_OARB_PENDING 0x0086
+#define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 1
+#define regDAGB0_WRCLI_ASK2ARB_PENDING 0x0087
+#define regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX 1
+#define regDAGB0_WRCLI_ASK2DF_PENDING 0x0088
+#define regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX 1
+#define regDAGB0_WRCLI_OSD_PENDING 0x0089
+#define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 1
+#define regDAGB0_WRCLI_ASK_OSD_PENDING 0x008a
+#define regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX 1
+#define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x008b
+#define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1
+#define regDAGB0_WRCLI_DBUS_GO_PENDING 0x008c
+#define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 1
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x008d
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x008e
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1
+#define regDAGB0_DAGB_DLY 0x008f
+#define regDAGB0_DAGB_DLY_BASE_IDX 1
+#define regDAGB0_CNTL_MISC 0x0090
+#define regDAGB0_CNTL_MISC_BASE_IDX 1
+#define regDAGB0_CNTL_MISC2 0x0091
+#define regDAGB0_CNTL_MISC2_BASE_IDX 1
+#define regDAGB0_FIFO_EMPTY 0x0092
+#define regDAGB0_FIFO_EMPTY_BASE_IDX 1
+#define regDAGB0_FIFO_FULL 0x0093
+#define regDAGB0_FIFO_FULL_BASE_IDX 1
+#define regDAGB0_RD_CREDITS_FULL 0x0094
+#define regDAGB0_RD_CREDITS_FULL_BASE_IDX 1
+#define regDAGB0_WR_CREDITS_FULL 0x0095
+#define regDAGB0_WR_CREDITS_FULL_BASE_IDX 1
+#define regDAGB0_PERFCOUNTER_LO 0x0096
+#define regDAGB0_PERFCOUNTER_LO_BASE_IDX 1
+#define regDAGB0_PERFCOUNTER_HI 0x0097
+#define regDAGB0_PERFCOUNTER_HI_BASE_IDX 1
+#define regDAGB0_PERFCOUNTER0_CFG 0x0098
+#define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 1
+#define regDAGB0_PERFCOUNTER1_CFG 0x0099
+#define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 1
+#define regDAGB0_PERFCOUNTER2_CFG 0x009a
+#define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 1
+#define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x009b
+#define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
+#define regDAGB0_L1TLB_REG_RW 0x009c
+#define regDAGB0_L1TLB_REG_RW_BASE_IDX 1
+#define regDAGB0_RESERVE1 0x009d
+#define regDAGB0_RESERVE1_BASE_IDX 1
+#define regDAGB0_RESERVE2 0x009e
+#define regDAGB0_RESERVE2_BASE_IDX 1
+#define regDAGB0_RESERVE3 0x009f
+#define regDAGB0_RESERVE3_BASE_IDX 1
+#define regDAGB0_RESERVE4 0x00a0
+#define regDAGB0_RESERVE4_BASE_IDX 1
+#define regDAGB0_SDP_RD_BW_CNTL 0x00a1
+#define regDAGB0_SDP_RD_BW_CNTL_BASE_IDX 1
+#define regDAGB0_SDP_PRIORITY_OVERRIDE 0x00a2
+#define regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX 1
+#define regDAGB0_SDP_RD_PRIORITY 0x00a3
+#define regDAGB0_SDP_RD_PRIORITY_BASE_IDX 1
+#define regDAGB0_SDP_WR_PRIORITY 0x00a4
+#define regDAGB0_SDP_WR_PRIORITY_BASE_IDX 1
+#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP 0x00a5
+#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 1
+#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP 0x00a6
+#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX 1
+#define regDAGB0_SDP_ENABLE 0x00a7
+#define regDAGB0_SDP_ENABLE_BASE_IDX 1
+#define regDAGB0_SDP_CREDITS 0x00a8
+#define regDAGB0_SDP_CREDITS_BASE_IDX 1
+#define regDAGB0_SDP_TAG_RESERVE0 0x00a9
+#define regDAGB0_SDP_TAG_RESERVE0_BASE_IDX 1
+#define regDAGB0_SDP_TAG_RESERVE1 0x00aa
+#define regDAGB0_SDP_TAG_RESERVE1_BASE_IDX 1
+#define regDAGB0_SDP_VCC_RESERVE0 0x00ab
+#define regDAGB0_SDP_VCC_RESERVE0_BASE_IDX 1
+#define regDAGB0_SDP_VCC_RESERVE1 0x00ac
+#define regDAGB0_SDP_VCC_RESERVE1_BASE_IDX 1
+#define regDAGB0_SDP_ERR_STATUS 0x00ad
+#define regDAGB0_SDP_ERR_STATUS_BASE_IDX 1
+#define regDAGB0_SDP_REQ_CNTL 0x00ae
+#define regDAGB0_SDP_REQ_CNTL_BASE_IDX 1
+#define regDAGB0_SDP_MISC_AON 0x00af
+#define regDAGB0_SDP_MISC_AON_BASE_IDX 1
+#define regDAGB0_SDP_MISC 0x00b0
+#define regDAGB0_SDP_MISC_BASE_IDX 1
+#define regDAGB0_SDP_MISC2 0x00b1
+#define regDAGB0_SDP_MISC2_BASE_IDX 1
+#define regDAGB0_SDP_VCD_RESERVE0 0x00b3
+#define regDAGB0_SDP_VCD_RESERVE0_BASE_IDX 1
+#define regDAGB0_SDP_VCD_RESERVE1 0x00b4
+#define regDAGB0_SDP_VCD_RESERVE1_BASE_IDX 1
+#define regDAGB0_SDP_ARB_CNTL0 0x00b5
+#define regDAGB0_SDP_ARB_CNTL0_BASE_IDX 1
+#define regDAGB0_SDP_ARB_CNTL1 0x00b6
+#define regDAGB0_SDP_ARB_CNTL1_BASE_IDX 1
+#define regDAGB0_SDP_CGTT_CLK_CTRL 0x00b7
+#define regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX 1
+#define regDAGB0_SDP_LATENCY_SAMPLING 0x00b8
+#define regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX 1
+
+
+// addressBlock: mmhub_pctldec
+// base address: 0x68e00
+#define regPCTL_CTRL 0x0380
+#define regPCTL_CTRL_BASE_IDX 1
+#define regPCTL_MMHUB_DEEPSLEEP_IB 0x0381
+#define regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX 1
+#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382
+#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1
+#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0383
+#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1
+#define regPCTL_PG_IGNORE_DEEPSLEEP 0x0384
+#define regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 1
+#define regPCTL_PG_IGNORE_DEEPSLEEP_IB 0x0385
+#define regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1
+#define regPCTL_SLICE0_CFG_DAGB_WRBUSY 0x0386
+#define regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX 1
+#define regPCTL_SLICE0_CFG_DAGB_RDBUSY 0x0387
+#define regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX 1
+#define regPCTL_SLICE0_CFG_DS_ALLOW 0x0388
+#define regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX 1
+#define regPCTL_SLICE0_CFG_DS_ALLOW_IB 0x0389
+#define regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1
+#define regPCTL_SLICE1_CFG_DAGB_WRBUSY 0x038a
+#define regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX 1
+#define regPCTL_SLICE1_CFG_DAGB_RDBUSY 0x038b
+#define regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX 1
+#define regPCTL_SLICE1_CFG_DS_ALLOW 0x038c
+#define regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX 1
+#define regPCTL_SLICE1_CFG_DS_ALLOW_IB 0x038d
+#define regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1
+#define regPCTL_UTCL2_MISC 0x038e
+#define regPCTL_UTCL2_MISC_BASE_IDX 1
+#define regPCTL_SLICE0_MISC 0x038f
+#define regPCTL_SLICE0_MISC_BASE_IDX 1
+#define regPCTL_SLICE1_MISC 0x0390
+#define regPCTL_SLICE1_MISC_BASE_IDX 1
+#define regPCTL_RENG_CTRL 0x0391
+#define regPCTL_RENG_CTRL_BASE_IDX 1
+#define regPCTL_UTCL2_RENG_EXECUTE 0x0392
+#define regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX 1
+#define regPCTL_SLICE0_RENG_EXECUTE 0x0393
+#define regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX 1
+#define regPCTL_SLICE1_RENG_EXECUTE 0x0394
+#define regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX 1
+#define regPCTL_UTCL2_RENG_RAM_INDEX 0x0395
+#define regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX 1
+#define regPCTL_UTCL2_RENG_RAM_DATA 0x0396
+#define regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX 1
+#define regPCTL_SLICE0_RENG_RAM_INDEX 0x0397
+#define regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX 1
+#define regPCTL_SLICE0_RENG_RAM_DATA 0x0398
+#define regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX 1
+#define regPCTL_SLICE1_RENG_RAM_INDEX 0x0399
+#define regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX 1
+#define regPCTL_SLICE1_RENG_RAM_DATA 0x039a
+#define regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX 1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x039b
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x039c
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x039d
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x039e
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x039f
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a0
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a1
+#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x03a2
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x03a3
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x03a4
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x03a5
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x03a6
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a7
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a8
+#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x03a9
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x03aa
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x03ab
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x03ac
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x03ad
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03ae
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03af
+#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1
+#define regPCTL_STATUS 0x03b0
+#define regPCTL_STATUS_BASE_IDX 1
+#define regPCTL_PERFCOUNTER_LO 0x03b1
+#define regPCTL_PERFCOUNTER_LO_BASE_IDX 1
+#define regPCTL_PERFCOUNTER_HI 0x03b2
+#define regPCTL_PERFCOUNTER_HI_BASE_IDX 1
+#define regPCTL_PERFCOUNTER0_CFG 0x03b3
+#define regPCTL_PERFCOUNTER0_CFG_BASE_IDX 1
+#define regPCTL_PERFCOUNTER1_CFG 0x03b4
+#define regPCTL_PERFCOUNTER1_CFG_BASE_IDX 1
+#define regPCTL_PERFCOUNTER_RSLT_CNTL 0x03b5
+#define regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
+#define regPCTL_RESERVED_0 0x03b6
+#define regPCTL_RESERVED_0_BASE_IDX 1
+#define regPCTL_RESERVED_1 0x03b7
+#define regPCTL_RESERVED_1_BASE_IDX 1
+#define regPCTL_RESERVED_2 0x03b8
+#define regPCTL_RESERVED_2_BASE_IDX 1
+#define regPCTL_RESERVED_3 0x03b9
+#define regPCTL_RESERVED_3_BASE_IDX 1
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1pfdec
+// base address: 0x69600
+#define regMMMC_VM_MX_L1_TLB0_STATUS 0x0588
+#define regMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLB1_STATUS 0x0589
+#define regMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLB2_STATUS 0x058a
+#define regMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLB3_STATUS 0x058b
+#define regMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLB4_STATUS 0x058c
+#define regMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLB5_STATUS 0x058d
+#define regMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLB6_STATUS 0x058e
+#define regMMMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLB7_STATUS 0x058f
+#define regMMMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 1
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1pldec
+// base address: 0x69670
+#define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG 0x059c
+#define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 1
+#define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG 0x059d
+#define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 1
+#define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG 0x059e
+#define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 1
+#define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG 0x059f
+#define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 1
+#define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x05a0
+#define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1prdec
+// base address: 0x69690
+#define regMMMC_VM_MX_L1_PERFCOUNTER_LO 0x05a4
+#define regMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 1
+#define regMMMC_VM_MX_L1_PERFCOUNTER_HI 0x05a5
+#define regMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 1
+
+
+// addressBlock: mmhub_l1tlb_mmvmtlspfdec
+// base address: 0x696c0
+#define regMMMC_VM_MX_L1_TLS0_CNTL 0x05b0
+#define regMMMC_VM_MX_L1_TLS0_CNTL_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL0 0x05b1
+#define regMMMC_VM_MX_L1_TLS0_CNTL0_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL1 0x05b2
+#define regMMMC_VM_MX_L1_TLS0_CNTL1_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL2 0x05b3
+#define regMMMC_VM_MX_L1_TLS0_CNTL2_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL3 0x05b4
+#define regMMMC_VM_MX_L1_TLS0_CNTL3_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL4 0x05b5
+#define regMMMC_VM_MX_L1_TLS0_CNTL4_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL5 0x05b6
+#define regMMMC_VM_MX_L1_TLS0_CNTL5_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL6 0x05b7
+#define regMMMC_VM_MX_L1_TLS0_CNTL6_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL7 0x05b8
+#define regMMMC_VM_MX_L1_TLS0_CNTL7_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL8 0x05b9
+#define regMMMC_VM_MX_L1_TLS0_CNTL8_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL9 0x05ba
+#define regMMMC_VM_MX_L1_TLS0_CNTL9_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL10 0x05bb
+#define regMMMC_VM_MX_L1_TLS0_CNTL10_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL11 0x05bc
+#define regMMMC_VM_MX_L1_TLS0_CNTL11_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL12 0x05bd
+#define regMMMC_VM_MX_L1_TLS0_CNTL12_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL13 0x05be
+#define regMMMC_VM_MX_L1_TLS0_CNTL13_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL14 0x05bf
+#define regMMMC_VM_MX_L1_TLS0_CNTL14_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL15 0x05c0
+#define regMMMC_VM_MX_L1_TLS0_CNTL15_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL16 0x05c1
+#define regMMMC_VM_MX_L1_TLS0_CNTL16_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL17 0x05c2
+#define regMMMC_VM_MX_L1_TLS0_CNTL17_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL18 0x05c3
+#define regMMMC_VM_MX_L1_TLS0_CNTL18_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL19 0x05c4
+#define regMMMC_VM_MX_L1_TLS0_CNTL19_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL20 0x05c5
+#define regMMMC_VM_MX_L1_TLS0_CNTL20_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL21 0x05c6
+#define regMMMC_VM_MX_L1_TLS0_CNTL21_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL22 0x05c7
+#define regMMMC_VM_MX_L1_TLS0_CNTL22_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL23 0x05c8
+#define regMMMC_VM_MX_L1_TLS0_CNTL23_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL24 0x05c9
+#define regMMMC_VM_MX_L1_TLS0_CNTL24_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL25 0x05ca
+#define regMMMC_VM_MX_L1_TLS0_CNTL25_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL26 0x05cb
+#define regMMMC_VM_MX_L1_TLS0_CNTL26_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL27 0x05cc
+#define regMMMC_VM_MX_L1_TLS0_CNTL27_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL28 0x05cd
+#define regMMMC_VM_MX_L1_TLS0_CNTL28_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL29 0x05ce
+#define regMMMC_VM_MX_L1_TLS0_CNTL29_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL30 0x05cf
+#define regMMMC_VM_MX_L1_TLS0_CNTL30_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL31 0x05d0
+#define regMMMC_VM_MX_L1_TLS0_CNTL31_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL32 0x05d1
+#define regMMMC_VM_MX_L1_TLS0_CNTL32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL33 0x05d2
+#define regMMMC_VM_MX_L1_TLS0_CNTL33_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL34 0x05d3
+#define regMMMC_VM_MX_L1_TLS0_CNTL34_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL35 0x05d4
+#define regMMMC_VM_MX_L1_TLS0_CNTL35_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL36 0x05d5
+#define regMMMC_VM_MX_L1_TLS0_CNTL36_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_CNTL37 0x05d6
+#define regMMMC_VM_MX_L1_TLS0_CNTL37_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32 0x05d7
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32 0x05d8
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32 0x05d9
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32 0x05da
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32 0x05db
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32 0x05dc
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32 0x05dd
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32 0x05de
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32 0x05df
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32 0x05e0
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32 0x05e1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32 0x05e2
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32 0x05e3
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32 0x05e4
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32 0x05e5
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32 0x05e6
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32 0x05e7
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32 0x05e8
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32 0x05e9
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32 0x05ea
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32 0x05eb
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32 0x05ec
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32 0x05ed
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32 0x05ee
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32 0x05ef
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32 0x05f0
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32 0x05f1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32 0x05f2
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32 0x05f3
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32 0x05f4
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32 0x05f5
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32 0x05f6
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32 0x05f7
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32 0x05f8
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32 0x05f9
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32 0x05fa
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32 0x05fb
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32 0x05fc
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32 0x05fd
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32 0x05fe
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32 0x05ff
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32 0x0600
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32 0x0601
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32 0x0602
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32 0x0603
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32 0x0604
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32 0x0605
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32 0x0606
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32 0x0607
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32 0x0608
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32 0x0609
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32 0x060a
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32 0x060b
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32 0x060c
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32 0x060d
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32 0x060e
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32 0x060f
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32 0x0610
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32 0x0611
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32 0x0612
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32 0x0613
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32 0x0614
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32 0x0615
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32 0x0616
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32 0x0617
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32 0x0618
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32 0x0619
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32 0x061a
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32 0x061b
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32 0x061c
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32 0x061d
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32 0x061e
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32 0x061f
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32 0x0620
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32 0x0621
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32 0x0622
+#define regMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32 0x0623
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32 0x0624
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32 0x0625
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32 0x0626
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32 0x0627
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32 0x0628
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32 0x0629
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32 0x062a
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32 0x062b
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32 0x062c
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32 0x062d
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32 0x062e
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32 0x062f
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32 0x0630
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32 0x0631
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32 0x0632
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32 0x0633
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32 0x0634
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32 0x0635
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32 0x0636
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32 0x0637
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32 0x0638
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32 0x0639
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32 0x063a
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32 0x063b
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32 0x063c
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32 0x063d
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32 0x063e
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32 0x063f
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32 0x0640
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32 0x0641
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32 0x0642
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32 0x0643
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32 0x0644
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32 0x0645
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32 0x0646
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32 0x0647
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32 0x0648
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32 0x0649
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32 0x064a
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32 0x064b
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32 0x064c
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32 0x064d
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32 0x064e
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32 0x064f
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32 0x0650
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32 0x0651
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32 0x0652
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32 0x0653
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32 0x0654
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32 0x0655
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32 0x0656
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32 0x0657
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32 0x0658
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32 0x0659
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32 0x065a
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32 0x065b
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32 0x065c
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32 0x065d
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32 0x065e
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32 0x065f
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32 0x0660
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32 0x0661
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32 0x0662
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32 0x0663
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32 0x0664
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32 0x0665
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32 0x0666
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32 0x0667
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32 0x0668
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32 0x0669
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32 0x066a
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32 0x066b
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32 0x066c
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32 0x066d
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32 0x066e
+#define regMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32 0x066f
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32 0x0670
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32 0x0671
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32 0x0672
+#define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS 0x0673
+#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32 0x0674
+#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32 0x0675
+#define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1
+#define regMMVM_L2_SAW_CNTL 0x0676
+#define regMMVM_L2_SAW_CNTL_BASE_IDX 1
+#define regMMVM_L2_SAW_CNTL2 0x0677
+#define regMMVM_L2_SAW_CNTL2_BASE_IDX 1
+#define regMMVM_L2_SAW_CNTL3 0x0678
+#define regMMVM_L2_SAW_CNTL3_BASE_IDX 1
+#define regMMVM_L2_SAW_CNTL4 0x0679
+#define regMMVM_L2_SAW_CNTL4_BASE_IDX 1
+#define regMMVM_L2_SAW_CONTEXT0_CNTL 0x067a
+#define regMMVM_L2_SAW_CONTEXT0_CNTL_BASE_IDX 1
+#define regMMVM_L2_SAW_CONTEXT0_CNTL2 0x067b
+#define regMMVM_L2_SAW_CONTEXT0_CNTL2_BASE_IDX 1
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x067c
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x067d
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x067e
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x067f
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0680
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0681
+#define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_L2_SAW_CONTEXTS_DISABLE 0x0682
+#define regMMVM_L2_SAW_CONTEXTS_DISABLE_BASE_IDX 1
+#define regMMVM_L2_SAW_PIPES_BUSY_LO32 0x0683
+#define regMMVM_L2_SAW_PIPES_BUSY_LO32_BASE_IDX 1
+#define regMMVM_L2_SAW_PIPES_BUSY_HI32 0x0684
+#define regMMVM_L2_SAW_PIPES_BUSY_HI32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS 0x0685
+#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32 0x0686
+#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32 0x0687
+#define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2dec
+// base address: 0x69b00
+#define regMM_ATC_L2_CNTL 0x06c0
+#define regMM_ATC_L2_CNTL_BASE_IDX 1
+#define regMM_ATC_L2_CNTL2 0x06c1
+#define regMM_ATC_L2_CNTL2_BASE_IDX 1
+#define regMM_ATC_L2_CACHE_DATA0 0x06c4
+#define regMM_ATC_L2_CACHE_DATA0_BASE_IDX 1
+#define regMM_ATC_L2_CACHE_DATA1 0x06c5
+#define regMM_ATC_L2_CACHE_DATA1_BASE_IDX 1
+#define regMM_ATC_L2_CACHE_DATA2 0x06c6
+#define regMM_ATC_L2_CACHE_DATA2_BASE_IDX 1
+#define regMM_ATC_L2_CNTL3 0x06c7
+#define regMM_ATC_L2_CNTL3_BASE_IDX 1
+#define regMM_ATC_L2_CNTL4 0x06c8
+#define regMM_ATC_L2_CNTL4_BASE_IDX 1
+#define regMM_ATC_L2_CNTL5 0x06c9
+#define regMM_ATC_L2_CNTL5_BASE_IDX 1
+#define regMM_ATC_L2_MM_GROUP_RT_CLASSES 0x06ca
+#define regMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1
+#define regMM_ATC_L2_STATUS 0x06cb
+#define regMM_ATC_L2_STATUS_BASE_IDX 1
+#define regMM_ATC_L2_STATUS2 0x06cc
+#define regMM_ATC_L2_STATUS2_BASE_IDX 1
+#define regMM_ATC_L2_MISC_CG 0x06cd
+#define regMM_ATC_L2_MISC_CG_BASE_IDX 1
+#define regMM_ATC_L2_MEM_POWER_LS 0x06ce
+#define regMM_ATC_L2_MEM_POWER_LS_BASE_IDX 1
+#define regMM_ATC_L2_CGTT_CLK_CTRL 0x06cf
+#define regMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1
+#define regMM_ATC_L2_SDPPORT_CTRL 0x06d2
+#define regMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pfdec
+// base address: 0x69c00
+#define regMMVM_L2_CNTL 0x0700
+#define regMMVM_L2_CNTL_BASE_IDX 1
+#define regMMVM_L2_CNTL2 0x0701
+#define regMMVM_L2_CNTL2_BASE_IDX 1
+#define regMMVM_L2_CNTL3 0x0702
+#define regMMVM_L2_CNTL3_BASE_IDX 1
+#define regMMVM_L2_STATUS 0x0703
+#define regMMVM_L2_STATUS_BASE_IDX 1
+#define regMMVM_DUMMY_PAGE_FAULT_CNTL 0x0704
+#define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1
+#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0705
+#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1
+#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0706
+#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_CNTL 0x0707
+#define regMMVM_INVALIDATE_CNTL_BASE_IDX 1
+#define regMMVM_L2_PROTECTION_FAULT_CNTL 0x0708
+#define regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 1
+#define regMMVM_L2_PROTECTION_FAULT_CNTL2 0x0709
+#define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1
+#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x070a
+#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 1
+#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x070b
+#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 1
+#define regMMVM_L2_PROTECTION_FAULT_STATUS 0x070c
+#define regMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 1
+#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x070d
+#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1
+#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x070e
+#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1
+#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x070f
+#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1
+#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0710
+#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0712
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0713
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0714
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0715
+#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1
+#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0716
+#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1
+#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0717
+#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1
+#define regMMVM_L2_CNTL4 0x0718
+#define regMMVM_L2_CNTL4_BASE_IDX 1
+#define regMMVM_L2_MM_GROUP_RT_CLASSES 0x0719
+#define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1
+#define regMMVM_L2_BANK_SELECT_RESERVED_CID 0x071a
+#define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1
+#define regMMVM_L2_BANK_SELECT_RESERVED_CID2 0x071b
+#define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1
+#define regMMVM_L2_CACHE_PARITY_CNTL 0x071c
+#define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 1
+#define regMMVM_L2_CGTT_CLK_CTRL 0x071d
+#define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 1
+#define regMMVM_L2_CNTL5 0x071e
+#define regMMVM_L2_CNTL5_BASE_IDX 1
+#define regMMVM_L2_GCR_CNTL 0x071f
+#define regMMVM_L2_GCR_CNTL_BASE_IDX 1
+#define regMMVM_L2_CGTT_BUSY_CTRL 0x0720
+#define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX 1
+#define regMMVM_L2_PTE_CACHE_DUMP_CNTL 0x0721
+#define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 1
+#define regMMVM_L2_PTE_CACHE_DUMP_READ 0x0722
+#define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 1
+#define regMMVM_L2_BANK_SELECT_MASKS 0x0725
+#define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX 1
+#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x0726
+#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 1
+#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x0727
+#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 1
+#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x0728
+#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 1
+#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x0729
+#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 1
+#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x072a
+#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2vcdec
+// base address: 0x69d00
+#define regMMVM_CONTEXT0_CNTL 0x0740
+#define regMMVM_CONTEXT0_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXT1_CNTL 0x0741
+#define regMMVM_CONTEXT1_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXT2_CNTL 0x0742
+#define regMMVM_CONTEXT2_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXT3_CNTL 0x0743
+#define regMMVM_CONTEXT3_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXT4_CNTL 0x0744
+#define regMMVM_CONTEXT4_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXT5_CNTL 0x0745
+#define regMMVM_CONTEXT5_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXT6_CNTL 0x0746
+#define regMMVM_CONTEXT6_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXT7_CNTL 0x0747
+#define regMMVM_CONTEXT7_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXT8_CNTL 0x0748
+#define regMMVM_CONTEXT8_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXT9_CNTL 0x0749
+#define regMMVM_CONTEXT9_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXT10_CNTL 0x074a
+#define regMMVM_CONTEXT10_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXT11_CNTL 0x074b
+#define regMMVM_CONTEXT11_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXT12_CNTL 0x074c
+#define regMMVM_CONTEXT12_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXT13_CNTL 0x074d
+#define regMMVM_CONTEXT13_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXT14_CNTL 0x074e
+#define regMMVM_CONTEXT14_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXT15_CNTL 0x074f
+#define regMMVM_CONTEXT15_CNTL_BASE_IDX 1
+#define regMMVM_CONTEXTS_DISABLE 0x0750
+#define regMMVM_CONTEXTS_DISABLE_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG0_SEM 0x0751
+#define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG1_SEM 0x0752
+#define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG2_SEM 0x0753
+#define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG3_SEM 0x0754
+#define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG4_SEM 0x0755
+#define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG5_SEM 0x0756
+#define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG6_SEM 0x0757
+#define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG7_SEM 0x0758
+#define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG8_SEM 0x0759
+#define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG9_SEM 0x075a
+#define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG10_SEM 0x075b
+#define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG11_SEM 0x075c
+#define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG12_SEM 0x075d
+#define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG13_SEM 0x075e
+#define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG14_SEM 0x075f
+#define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG15_SEM 0x0760
+#define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG16_SEM 0x0761
+#define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG17_SEM 0x0762
+#define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG0_REQ 0x0763
+#define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG1_REQ 0x0764
+#define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG2_REQ 0x0765
+#define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG3_REQ 0x0766
+#define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG4_REQ 0x0767
+#define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG5_REQ 0x0768
+#define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG6_REQ 0x0769
+#define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG7_REQ 0x076a
+#define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG8_REQ 0x076b
+#define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG9_REQ 0x076c
+#define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG10_REQ 0x076d
+#define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG11_REQ 0x076e
+#define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG12_REQ 0x076f
+#define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG13_REQ 0x0770
+#define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG14_REQ 0x0771
+#define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG15_REQ 0x0772
+#define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG16_REQ 0x0773
+#define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG17_REQ 0x0774
+#define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG0_ACK 0x0775
+#define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG1_ACK 0x0776
+#define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG2_ACK 0x0777
+#define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG3_ACK 0x0778
+#define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG4_ACK 0x0779
+#define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG5_ACK 0x077a
+#define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG6_ACK 0x077b
+#define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG7_ACK 0x077c
+#define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG8_ACK 0x077d
+#define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG9_ACK 0x077e
+#define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG10_ACK 0x077f
+#define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG11_ACK 0x0780
+#define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG12_ACK 0x0781
+#define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG13_ACK 0x0782
+#define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG14_ACK 0x0783
+#define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG15_ACK 0x0784
+#define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG16_ACK 0x0785
+#define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG17_ACK 0x0786
+#define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0787
+#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0788
+#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0789
+#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x078a
+#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x078b
+#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x078c
+#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x078d
+#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x078e
+#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x078f
+#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0790
+#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0791
+#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0792
+#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0793
+#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0794
+#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0795
+#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0796
+#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0797
+#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0798
+#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0799
+#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x079a
+#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x079b
+#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x079c
+#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x079d
+#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x079e
+#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x079f
+#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x07a0
+#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x07a1
+#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x07a2
+#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x07a3
+#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x07a4
+#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x07a5
+#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x07a6
+#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x07a7
+#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x07a8
+#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x07a9
+#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1
+#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x07aa
+#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x07ab
+#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x07ac
+#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x07ad
+#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x07ae
+#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x07af
+#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x07b0
+#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x07b1
+#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x07b2
+#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x07b3
+#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x07b4
+#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x07b5
+#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x07b6
+#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x07b7
+#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x07b8
+#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x07b9
+#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x07ba
+#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x07bb
+#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x07bc
+#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x07bd
+#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x07be
+#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x07bf
+#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x07c0
+#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x07c1
+#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x07c2
+#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x07c3
+#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x07c4
+#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x07c5
+#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x07c6
+#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x07c7
+#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x07c8
+#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x07c9
+#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x07ca
+#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x07cb
+#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x07cc
+#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x07cd
+#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x07ce
+#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x07cf
+#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x07d0
+#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x07d1
+#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x07d2
+#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x07d3
+#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x07d4
+#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x07d5
+#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x07d6
+#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x07d7
+#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x07d8
+#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x07d9
+#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x07da
+#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x07db
+#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x07dc
+#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x07dd
+#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x07de
+#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x07df
+#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x07e0
+#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x07e1
+#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x07e2
+#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x07e3
+#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x07e4
+#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x07e5
+#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x07e6
+#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x07e7
+#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x07e8
+#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x07e9
+#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x07ea
+#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x07eb
+#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x07ec
+#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x07ed
+#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x07ee
+#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x07ef
+#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x07f0
+#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x07f1
+#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x07f2
+#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x07f3
+#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x07f4
+#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x07f5
+#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x07f6
+#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x07f7
+#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x07f8
+#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x07f9
+#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x07fa
+#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x07fb
+#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x07fc
+#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x07fd
+#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x07fe
+#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x07ff
+#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0800
+#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0801
+#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0802
+#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0803
+#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0804
+#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0805
+#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0806
+#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0807
+#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0808
+#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0809
+#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
+#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x080a
+#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
+#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080b
+#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080c
+#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080d
+#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080e
+#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x080f
+#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0810
+#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0811
+#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0812
+#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0813
+#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0814
+#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0815
+#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0816
+#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0817
+#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0818
+#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0819
+#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x081a
+#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x081b
+#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pldec
+// base address: 0x6a090
+#define regMMMC_VM_L2_PERFCOUNTER0_CFG 0x0824
+#define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1
+#define regMMMC_VM_L2_PERFCOUNTER1_CFG 0x0825
+#define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1
+#define regMMMC_VM_L2_PERFCOUNTER2_CFG 0x0826
+#define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1
+#define regMMMC_VM_L2_PERFCOUNTER3_CFG 0x0827
+#define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1
+#define regMMMC_VM_L2_PERFCOUNTER4_CFG 0x0828
+#define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1
+#define regMMMC_VM_L2_PERFCOUNTER5_CFG 0x0829
+#define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1
+#define regMMMC_VM_L2_PERFCOUNTER6_CFG 0x082a
+#define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1
+#define regMMMC_VM_L2_PERFCOUNTER7_CFG 0x082b
+#define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1
+#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x082c
+#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
+#define regMMUTCL2_PERFCOUNTER0_CFG 0x082d
+#define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX 1
+#define regMMUTCL2_PERFCOUNTER1_CFG 0x082e
+#define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX 1
+#define regMMUTCL2_PERFCOUNTER2_CFG 0x082f
+#define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX 1
+#define regMMUTCL2_PERFCOUNTER3_CFG 0x0830
+#define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX 1
+#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL 0x0831
+#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2prdec
+// base address: 0x6a0e0
+#define regMMMC_VM_L2_PERFCOUNTER_LO 0x0838
+#define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1
+#define regMMMC_VM_L2_PERFCOUNTER_HI 0x0839
+#define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1
+#define regMMUTCL2_PERFCOUNTER_LO 0x083a
+#define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX 1
+#define regMMUTCL2_PERFCOUNTER_HI 0x083b
+#define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec
+// base address: 0x6a130
+#define regMMVM_PCIE_ATS_CNTL 0x084c
+#define regMMVM_PCIE_ATS_CNTL_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
+// base address: 0x6a340
+#define regMMMC_VM_NB_MMIOBASE 0x08d0
+#define regMMMC_VM_NB_MMIOBASE_BASE_IDX 1
+#define regMMMC_VM_NB_MMIOLIMIT 0x08d1
+#define regMMMC_VM_NB_MMIOLIMIT_BASE_IDX 1
+#define regMMMC_VM_NB_PCI_CTRL 0x08d2
+#define regMMMC_VM_NB_PCI_CTRL_BASE_IDX 1
+#define regMMMC_VM_NB_PCI_ARB 0x08d3
+#define regMMMC_VM_NB_PCI_ARB_BASE_IDX 1
+#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x08d4
+#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1
+#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x08d5
+#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1
+#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x08d6
+#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1
+#define regMMMC_VM_FB_OFFSET 0x08d7
+#define regMMMC_VM_FB_OFFSET_BASE_IDX 1
+#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x08d8
+#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1
+#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x08d9
+#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1
+#define regMMMC_VM_STEERING 0x08da
+#define regMMMC_VM_STEERING_BASE_IDX 1
+#define regMMMC_SHARED_VIRT_RESET_REQ 0x08db
+#define regMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 1
+#define regMMMC_MEM_POWER_LS 0x08dc
+#define regMMMC_MEM_POWER_LS_BASE_IDX 1
+#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x08dd
+#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1
+#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x08de
+#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1
+#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x08df
+#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 1
+#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x08e0
+#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 1
+#define regMMMC_VM_APT_CNTL 0x08e1
+#define regMMMC_VM_APT_CNTL_BASE_IDX 1
+#define regMMMC_VM_LOCAL_FB_ADDRESS_START 0x08e2
+#define regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 1
+#define regMMMC_VM_LOCAL_FB_ADDRESS_END 0x08e3
+#define regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 1
+#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x08e4
+#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 1
+#define regMMUTCL2_CGTT_CLK_CTRL 0x08e5
+#define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 1
+#define regMMMC_SHARED_ACTIVE_FCN_ID 0x08e6
+#define regMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1
+#define regMMUTCL2_CGTT_BUSY_CTRL 0x08e7
+#define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 1
+#define regMMUTCL2_HARVEST_BYPASS_GROUPS 0x08e8
+#define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 1
+#define regMMUTCL2_GROUP_RET_FAULT_STATUS 0x08ea
+#define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec
+// base address: 0x6a3b0
+#define regMMMC_VM_FB_LOCATION_BASE 0x08ec
+#define regMMMC_VM_FB_LOCATION_BASE_BASE_IDX 1
+#define regMMMC_VM_FB_LOCATION_TOP 0x08ed
+#define regMMMC_VM_FB_LOCATION_TOP_BASE_IDX 1
+#define regMMMC_VM_AGP_TOP 0x08ee
+#define regMMMC_VM_AGP_TOP_BASE_IDX 1
+#define regMMMC_VM_AGP_BOT 0x08ef
+#define regMMMC_VM_AGP_BOT_BASE_IDX 1
+#define regMMMC_VM_AGP_BASE 0x08f0
+#define regMMMC_VM_AGP_BASE_BASE_IDX 1
+#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x08f1
+#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1
+#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08f2
+#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1
+#define regMMMC_VM_MX_L1_TLB_CNTL 0x08f3
+#define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec
+// base address: 0x6a400
+#define regMM_ATC_L2_PERFCOUNTER_LO 0x0900
+#define regMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1
+#define regMM_ATC_L2_PERFCOUNTER_HI 0x0901
+#define regMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec
+// base address: 0x6a420
+#define regMM_ATC_L2_PERFCOUNTER0_CFG 0x0908
+#define regMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1
+#define regMM_ATC_L2_PERFCOUNTER1_CFG 0x0909
+#define regMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1
+#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x090a
+#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pspdec
+// base address: 0x6aa50
+#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID 0x0a94
+#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 1
+#define regMMVM_IOMMU_CONTROL_REGISTER 0x0a97
+#define regMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1
+#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0a98
+#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1
+#define regMMUTC_TRANSLATION_FAULT_CNTL0 0x0a99
+#define regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 1
+#define regMMUTC_TRANSLATION_FAULT_CNTL1 0x0a9a
+#define regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpspdec
+// base address: 0x6aa80
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x0aa0
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pspdec
+// base address: 0x6aa90
+#define regMM_ATC_L2_IOV_MODE_CNTL 0x0aa4
+#define regMM_ATC_L2_IOV_MODE_CNTL_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpfdec
+// base address: 0x6aac0
+#define regMML2TLB_TLB0_STATUS 0x0ab1
+#define regMML2TLB_TLB0_STATUS_BASE_IDX 1
+#define regMML2TLB_TMZ_CNTL 0x0ab2
+#define regMML2TLB_TMZ_CNTL_BASE_IDX 1
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x0ab3
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 1
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0ab4
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 1
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0ab5
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 1
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0ab6
+#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 1
+#define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ 0x0ab7
+#define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpldec
+// base address: 0x6ab00
+#define regMML2TLB_PERFCOUNTER0_CFG 0x0ac0
+#define regMML2TLB_PERFCOUNTER0_CFG_BASE_IDX 1
+#define regMML2TLB_PERFCOUNTER1_CFG 0x0ac1
+#define regMML2TLB_PERFCOUNTER1_CFG_BASE_IDX 1
+#define regMML2TLB_PERFCOUNTER2_CFG 0x0ac2
+#define regMML2TLB_PERFCOUNTER2_CFG_BASE_IDX 1
+#define regMML2TLB_PERFCOUNTER3_CFG 0x0ac3
+#define regMML2TLB_PERFCOUNTER3_CFG_BASE_IDX 1
+#define regMML2TLB_PERFCOUNTER_RSLT_CNTL 0x0ac4
+#define regMML2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbprdec
+// base address: 0x6ab20
+#define regMML2TLB_PERFCOUNTER_LO 0x0ac8
+#define regMML2TLB_PERFCOUNTER_LO_BASE_IDX 1
+#define regMML2TLB_PERFCOUNTER_HI 0x0ac9
+#define regMML2TLB_PERFCOUNTER_HI_BASE_IDX 1
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h
new file mode 100644
index 000000000000..f949666f0667
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h
@@ -0,0 +1,7483 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _mmhub_3_0_1_SH_MASK_HEADER
+#define _mmhub_3_0_1_SH_MASK_HEADER
+
+
+// addressBlock: mmhub_dagbdec
+//DAGB0_RDCLI0
+#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI1
+#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI2
+#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI3
+#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI4
+#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI5
+#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI6
+#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI7
+#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI8
+#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI9
+#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI10
+#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI11
+#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI12
+#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI13
+#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI14
+#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI15
+#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI16
+#define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI17
+#define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI18
+#define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI19
+#define DAGB0_RDCLI19__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI19__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI19__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI19__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI19__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI19__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI20
+#define DAGB0_RDCLI20__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI20__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI20__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI20__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI20__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI20__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI21
+#define DAGB0_RDCLI21__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI21__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI21__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI21__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI21__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI21__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI22
+#define DAGB0_RDCLI22__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI22__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI22__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI22__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI22__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI22__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI23
+#define DAGB0_RDCLI23__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI23__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI23__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI23__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI23__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI23__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI24
+#define DAGB0_RDCLI24__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI24__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI24__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI24__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI24__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI24__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI24__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI24__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI24__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI24__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI24__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI24__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI24__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI24__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI24__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI24__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI24__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI25
+#define DAGB0_RDCLI25__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI25__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI25__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI25__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI25__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI25__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI25__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI25__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI25__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI25__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI25__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI25__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI25__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI25__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI25__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI25__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI25__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI26
+#define DAGB0_RDCLI26__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI26__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI26__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI26__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI26__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI26__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI26__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI26__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI26__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI26__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI26__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI26__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI26__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI26__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI26__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI26__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI26__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI27
+#define DAGB0_RDCLI27__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI27__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI27__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI27__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI27__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI27__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI27__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI27__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI27__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI27__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI27__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI27__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI27__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI27__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI27__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI27__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI27__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI28
+#define DAGB0_RDCLI28__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI28__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI28__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI28__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI28__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI28__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI28__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI28__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI28__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI28__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI28__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI28__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI28__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI28__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI28__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI28__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI28__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI29
+#define DAGB0_RDCLI29__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI29__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI29__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI29__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI29__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI29__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI29__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI29__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI29__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI29__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI29__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI29__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI29__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI29__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI29__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI29__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI29__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RD_CNTL
+#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0
+#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6
+#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0xc
+#define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xf
+#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL
+#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L
+#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x00007000L
+#define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK 0x00008000L
+//DAGB0_RD_IO_CNTL
+#define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0
+#define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1
+#define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4
+#define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9
+#define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa
+#define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd
+#define DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12
+#define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L
+#define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL
+#define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L
+#define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L
+#define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L
+#define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L
+#define DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L
+//DAGB0_RD_GMI_CNTL
+#define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0
+#define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1
+#define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4
+#define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9
+#define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa
+#define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd
+#define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12
+#define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L
+#define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL
+#define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L
+#define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L
+#define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L
+#define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L
+#define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L
+//DAGB0_RD_ADDR_DAGB
+#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
+#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+#define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
+//DAGB0_RD_CGTT_CLK_CTRL
+#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e
+#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f
+#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL
+#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L
+//DAGB0_L1TLB_RD_CGTT_CLK_CTRL
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST1
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST2
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER2
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST3
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER3
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L
+//DAGB0_RD_VC0_CNTL
+#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC1_CNTL
+#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC2_CNTL
+#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC3_CNTL
+#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC4_CNTL
+#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC5_CNTL
+#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_IO_VC_CNTL
+#define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0
+#define DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L
+#define DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_GMI_VC_CNTL
+#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0
+#define DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L
+#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_CNTL_MISC
+#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x6
+#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK 0x000001C0L
+//DAGB0_RD_TLB_CREDIT
+#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB0_RDCLI_ASK_PENDING
+#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_GO_PENDING
+#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_GBLSEND_PENDING
+#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_TLB_PENDING
+#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_OARB_PENDING
+#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_ASK2ARB_PENDING
+#define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_ASK2DF_PENDING
+#define DAGB0_RDCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_OSD_PENDING
+#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_ASK_OSD_PENDING
+#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI0
+#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI1
+#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI2
+#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI3
+#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI4
+#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI5
+#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI6
+#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI7
+#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI8
+#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI9
+#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI10
+#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI11
+#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI12
+#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI13
+#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI14
+#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI15
+#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI16
+#define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI17
+#define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI18
+#define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI19
+#define DAGB0_WRCLI19__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI19__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI19__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI19__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI19__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI19__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI20
+#define DAGB0_WRCLI20__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI20__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI20__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI20__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI20__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI20__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI21
+#define DAGB0_WRCLI21__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI21__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI21__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI21__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI21__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI21__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI22
+#define DAGB0_WRCLI22__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI22__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI22__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI22__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI22__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI22__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI23
+#define DAGB0_WRCLI23__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI23__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI23__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI23__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI23__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI23__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI24
+#define DAGB0_WRCLI24__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI24__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI24__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI24__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI24__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI24__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI24__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI24__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI24__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI24__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI24__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI24__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI24__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI24__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI24__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI24__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI24__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI25
+#define DAGB0_WRCLI25__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI25__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI25__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI25__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI25__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI25__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI25__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI25__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI25__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI25__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI25__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI25__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI25__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI25__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI25__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI25__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI25__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI26
+#define DAGB0_WRCLI26__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI26__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI26__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI26__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI26__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI26__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI26__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI26__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI26__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI26__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI26__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI26__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI26__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI26__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI26__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI26__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI26__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI27
+#define DAGB0_WRCLI27__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI27__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI27__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI27__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI27__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI27__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI27__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI27__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI27__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI27__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI27__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI27__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI27__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI27__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI27__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI27__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI27__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI28
+#define DAGB0_WRCLI28__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI28__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI28__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI28__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI28__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI28__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI28__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI28__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI28__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI28__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI28__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI28__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI28__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI28__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI28__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI28__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI28__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI29
+#define DAGB0_WRCLI29__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI29__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI29__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI29__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI29__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI29__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI29__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI29__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI29__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI29__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI29__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI29__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI29__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI29__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI29__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI29__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI29__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WR_CNTL
+#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0
+#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6
+#define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xc
+#define DAGB0_WR_CNTL__UPDATE_FED__SHIFT 0xd
+#define DAGB0_WR_CNTL__UPDATE_NACK__SHIFT 0xe
+#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL
+#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L
+#define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK 0x00001000L
+#define DAGB0_WR_CNTL__UPDATE_FED_MASK 0x00002000L
+#define DAGB0_WR_CNTL__UPDATE_NACK_MASK 0x00004000L
+//DAGB0_WR_IO_CNTL
+#define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0
+#define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1
+#define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4
+#define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9
+#define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa
+#define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd
+#define DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12
+#define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L
+#define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL
+#define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L
+#define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L
+#define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L
+#define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L
+#define DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L
+//DAGB0_WR_GMI_CNTL
+#define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0
+#define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1
+#define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4
+#define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9
+#define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa
+#define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd
+#define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12
+#define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L
+#define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL
+#define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L
+#define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L
+#define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L
+#define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L
+#define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L
+//DAGB0_WR_ADDR_DAGB
+#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
+#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+#define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
+//DAGB0_WR_CGTT_CLK_CTRL
+#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e
+#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f
+#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL
+#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L
+//DAGB0_L1TLB_WR_CGTT_CLK_CTRL
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST1
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST2
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER2
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST3
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER3
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB
+#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB0_WR_DATA_DAGB_MAX_BURST0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_MAX_BURST1
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER1
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_MAX_BURST2
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER2
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_MAX_BURST3
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER3
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L
+//DAGB0_WR_VC0_CNTL
+#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC1_CNTL
+#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC2_CNTL
+#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC3_CNTL
+#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC4_CNTL
+#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC5_CNTL
+#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_IO_VC_CNTL
+#define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0
+#define DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L
+#define DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_GMI_VC_CNTL
+#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0
+#define DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L
+#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_CNTL_MISC
+#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x6
+#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x000007C0L
+//DAGB0_WR_TLB_CREDIT
+#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB0_WR_DATA_CREDIT
+#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
+#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
+#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
+#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
+#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
+#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
+#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
+#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
+//DAGB0_WR_MISC_CREDIT
+#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
+#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
+#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
+#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
+//DAGB0_WR_DATA_FIFO_CREDIT_CNTL1
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L
+//DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x1a
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1b
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1c
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x03F00000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x04000000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x08000000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x10000000L
+//DAGB0_WRCLI_ASK_PENDING
+#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_GO_PENDING
+#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_GBLSEND_PENDING
+#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_TLB_PENDING
+#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_OARB_PENDING
+#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_ASK2ARB_PENDING
+#define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_ASK2DF_PENDING
+#define DAGB0_WRCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_OSD_PENDING
+#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_ASK_OSD_PENDING
+#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_DBUS_ASK_PENDING
+#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_DBUS_GO_PENDING
+#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB0_DAGB_DLY
+#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0
+#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8
+#define DAGB0_DAGB_DLY__POS__SHIFT 0x10
+#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL
+#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L
+#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L
+//DAGB0_CNTL_MISC
+#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0
+#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL
+//DAGB0_CNTL_MISC2
+#define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT 0x0
+#define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT 0x1
+#define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT 0x2
+#define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT 0x3
+#define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT 0x4
+#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0x5
+#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0x6
+#define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT 0x7
+#define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT 0x8
+#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x9
+#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0xa
+#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0xb
+#define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK 0x00000001L
+#define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK 0x00000002L
+#define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK 0x00000004L
+#define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK 0x00000008L
+#define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK 0x00000010L
+#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000020L
+#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000040L
+#define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK 0x00000080L
+#define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK 0x00000100L
+#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000200L
+#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000400L
+#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000800L
+//DAGB0_FIFO_EMPTY
+#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0
+#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x0001FFFFL
+//DAGB0_FIFO_FULL
+#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0
+#define DAGB0_FIFO_FULL__FULL_MASK 0x0000FFFFL
+//DAGB0_RD_CREDITS_FULL
+#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0000007FL
+//DAGB0_WR_CREDITS_FULL
+#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0001FFFFL
+//DAGB0_PERFCOUNTER_LO
+#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//DAGB0_PERFCOUNTER_HI
+#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//DAGB0_PERFCOUNTER0_CFG
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//DAGB0_PERFCOUNTER1_CFG
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//DAGB0_PERFCOUNTER2_CFG
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//DAGB0_PERFCOUNTER_RSLT_CNTL
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//DAGB0_L1TLB_REG_RW
+#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0
+#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1
+#define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT 0x2
+#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L
+#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L
+#define DAGB0_L1TLB_REG_RW__RESERVE_MASK 0x3FFFFFFCL
+//DAGB0_RESERVE1
+#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE2
+#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE3
+#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE4
+#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_SDP_RD_BW_CNTL
+#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0
+#define DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0x1
+#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0x9
+#define DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0xa
+#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0xd
+#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L
+#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK 0x000001FEL
+#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00000200L
+#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK 0x00001C00L
+#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x0007E000L
+//DAGB0_SDP_PRIORITY_OVERRIDE
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT 0x0
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT 0x4
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT 0x9
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT 0xa
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT 0xb
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT 0xc
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT 0xd
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT 0xe
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT 0x10
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT 0x14
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT 0x19
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT 0x1a
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT 0x1b
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT 0x1c
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT 0x1d
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT 0x1e
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK 0x0000000FL
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK 0x00000200L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK 0x00000400L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK 0x00000800L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK 0x00001000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK 0x00002000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK 0x00004000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK 0x000F0000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK 0x01F00000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK 0x02000000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK 0x04000000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK 0x08000000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK 0x10000000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK 0x20000000L
+#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK 0x40000000L
+//DAGB0_SDP_RD_PRIORITY
+#define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT 0x0
+#define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT 0x4
+#define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT 0x8
+#define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT 0xc
+#define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT 0x10
+#define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT 0x14
+#define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK 0x0000000FL
+#define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK 0x000000F0L
+#define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK 0x00000F00L
+#define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK 0x0000F000L
+#define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK 0x000F0000L
+#define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK 0x00F00000L
+//DAGB0_SDP_WR_PRIORITY
+#define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT 0x0
+#define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT 0x4
+#define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT 0x8
+#define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT 0xc
+#define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT 0x10
+#define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT 0x14
+#define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK 0x0000000FL
+#define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK 0x000000F0L
+#define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK 0x00000F00L
+#define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK 0x0000F000L
+#define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK 0x000F0000L
+#define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK 0x00F00000L
+//DAGB0_SDP_RD_CLI2SDP_VC_MAP
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L
+#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L
+//DAGB0_SDP_WR_CLI2SDP_VC_MAP
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L
+#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L
+//DAGB0_SDP_ENABLE
+#define DAGB0_SDP_ENABLE__ENABLE__SHIFT 0x0
+#define DAGB0_SDP_ENABLE__ENABLE_MASK 0x00000001L
+//DAGB0_SDP_CREDITS
+#define DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
+#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
+#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
+#define DAGB0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
+#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
+#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L
+//DAGB0_SDP_TAG_RESERVE0
+#define DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
+#define DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
+#define DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
+#define DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
+#define DAGB0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
+#define DAGB0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
+#define DAGB0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
+#define DAGB0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
+//DAGB0_SDP_TAG_RESERVE1
+#define DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
+#define DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
+#define DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
+#define DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
+#define DAGB0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
+#define DAGB0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
+#define DAGB0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
+#define DAGB0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
+//DAGB0_SDP_VCC_RESERVE0
+#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//DAGB0_SDP_VCC_RESERVE1
+#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//DAGB0_SDP_ERR_STATUS
+#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
+#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
+#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
+#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
+#define DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0xd
+#define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe
+#define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf
+#define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10
+#define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11
+#define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12
+#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
+#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
+#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
+#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
+#define DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
+#define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L
+#define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L
+#define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L
+#define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L
+#define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L
+//DAGB0_SDP_REQ_CNTL
+#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
+#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
+#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
+#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
+#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4
+#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5
+#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6
+#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8
+#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa
+#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
+#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
+#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
+#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
+#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L
+#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L
+#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L
+#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L
+#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L
+//DAGB0_SDP_MISC_AON
+#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0
+#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2
+#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L
+#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L
+//DAGB0_SDP_MISC
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7
+#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8
+#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9
+#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb
+#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd
+#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf
+#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14
+#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x15
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L
+#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L
+#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L
+#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L
+#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L
+#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L
+#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L
+#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00100000L
+#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00200000L
+//DAGB0_SDP_MISC2
+#define DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0
+#define DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1
+#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2
+#define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT 0x3
+#define DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L
+#define DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L
+#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L
+#define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK 0x00000008L
+//DAGB0_SDP_VCD_RESERVE0
+#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//DAGB0_SDP_VCD_RESERVE1
+#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x12
+#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x00040000L
+//DAGB0_SDP_ARB_CNTL0
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3
+#define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT 0x4
+#define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT 0x5
+#define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT 0x6
+#define DAGB0_SDP_ARB_CNTL0__DED_MODE__SHIFT 0x7
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L
+#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L
+#define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK 0x00000010L
+#define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK 0x00000020L
+#define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK 0x00000040L
+#define DAGB0_SDP_ARB_CNTL0__DED_MODE_MASK 0x00000080L
+//DAGB0_SDP_ARB_CNTL1
+#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0
+#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x8
+#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0x10
+#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x18
+#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00007F00L
+#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x007F0000L
+#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x7F000000L
+//DAGB0_SDP_CGTT_CLK_CTRL
+#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5
+#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd
+#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e
+#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f
+#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL
+#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L
+#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L
+#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L
+#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L
+//DAGB0_SDP_LATENCY_SAMPLING
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
+#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
+
+
+// addressBlock: mmhub_pctldec
+//PCTL_CTRL
+#define PCTL_CTRL__PG_ENABLE__SHIFT 0x0
+#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1
+#define PCTL_CTRL__RSMU_RDTIMER_ENABLE__SHIFT 0x4
+#define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD__SHIFT 0x5
+#define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x7
+#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xe
+#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x13
+#define PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT 0x14
+#define PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT 0x15
+#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT 0x16
+#define PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT 0x1b
+#define PCTL_CTRL__Z9_PWRDOWN__SHIFT 0x1c
+#define PCTL_CTRL__Z9_PWRUP__SHIFT 0x1d
+#define PCTL_CTRL__SNR_DISABLE__SHIFT 0x1e
+#define PCTL_CTRL__WRACK_GUARD__SHIFT 0x1f
+#define PCTL_CTRL__PG_ENABLE_MASK 0x00000001L
+#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL
+#define PCTL_CTRL__RSMU_RDTIMER_ENABLE_MASK 0x00000010L
+#define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD_MASK 0x00000060L
+#define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00003F80L
+#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0007C000L
+#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00080000L
+#define PCTL_CTRL__UTCL2_LEGACY_MODE_MASK 0x00100000L
+#define PCTL_CTRL__SDP_DISCONNECT_MODE_MASK 0x00200000L
+#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK 0x07C00000L
+#define PCTL_CTRL__ZSC_TIMER_ENABLE_MASK 0x08000000L
+#define PCTL_CTRL__Z9_PWRDOWN_MASK 0x10000000L
+#define PCTL_CTRL__Z9_PWRUP_MASK 0x20000000L
+#define PCTL_CTRL__SNR_DISABLE_MASK 0x40000000L
+#define PCTL_CTRL__WRACK_GUARD_MASK 0x80000000L
+//PCTL_MMHUB_DEEPSLEEP_IB
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10
+#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L
+#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L
+//PCTL_MMHUB_DEEPSLEEP_OVERRIDE
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L
+//PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L
+//PCTL_PG_IGNORE_DEEPSLEEP
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11
+#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L
+//PCTL_PG_IGNORE_DEEPSLEEP_IB
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L
+//PCTL_SLICE0_CFG_DAGB_WRBUSY
+#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0
+#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL
+//PCTL_SLICE0_CFG_DAGB_RDBUSY
+#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0
+#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL
+//PCTL_SLICE0_CFG_DS_ALLOW
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L
+//PCTL_SLICE0_CFG_DS_ALLOW_IB
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L
+//PCTL_SLICE1_CFG_DAGB_WRBUSY
+#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0
+#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL
+//PCTL_SLICE1_CFG_DAGB_RDBUSY
+#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0
+#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL
+//PCTL_SLICE1_CFG_DS_ALLOW
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L
+//PCTL_SLICE1_CFG_DS_ALLOW_IB
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L
+//PCTL_UTCL2_MISC
+#define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0
+#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb
+#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc
+#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf
+#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10
+#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11
+#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12
+#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13
+#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14
+#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a
+#define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000007FFL
+#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L
+#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L
+#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L
+#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L
+#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L
+#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L
+#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L
+#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L
+#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L
+//PCTL_SLICE0_MISC
+#define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0
+#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa
+#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb
+#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe
+#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf
+#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10
+#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11
+#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12
+#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13
+#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14
+#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a
+#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT 0x1e
+#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT 0x1f
+#define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL
+#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L
+#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L
+#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L
+#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L
+#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L
+#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L
+#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L
+#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L
+#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L
+#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L
+#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK 0x40000000L
+#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK 0x80000000L
+//PCTL_SLICE1_MISC
+#define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0
+#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa
+#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb
+#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe
+#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf
+#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10
+#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11
+#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12
+#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13
+#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14
+#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a
+#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT 0x1e
+#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT 0x1f
+#define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL
+#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L
+#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L
+#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L
+#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L
+#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L
+#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L
+#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L
+#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L
+#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L
+#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L
+#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK 0x40000000L
+#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK 0x80000000L
+//PCTL_RENG_CTRL
+#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT 0x0
+#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT 0x1
+#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK 0x00000001L
+#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L
+//PCTL_UTCL2_RENG_EXECUTE
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L
+//PCTL_SLICE0_RENG_EXECUTE
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L
+//PCTL_SLICE1_RENG_EXECUTE
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L
+//PCTL_UTCL2_RENG_RAM_INDEX
+#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
+#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL
+//PCTL_UTCL2_RENG_RAM_DATA
+#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
+#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL
+//PCTL_SLICE0_RENG_RAM_INDEX
+#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
+#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL
+//PCTL_SLICE0_RENG_RAM_DATA
+#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
+#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL
+//PCTL_SLICE1_RENG_RAM_INDEX
+#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
+#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL
+//PCTL_SLICE1_RENG_RAM_DATA
+#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
+#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L
+//PCTL_STATUS
+#define PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT 0x0
+#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT 0x1
+#define PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT 0x2
+#define PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT 0x3
+#define PCTL_STATUS__MMHUB_IDLE__SHIFT 0x4
+#define PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT 0x5
+#define PCTL_STATUS__RSMU_RDTIMEOUT_CNT__SHIFT 0x7
+#define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR__SHIFT 0xf
+#define PCTL_STATUS__MMHUB_POWER__SHIFT 0x10
+#define PCTL_STATUS__RENG_RAM_STALE__SHIFT 0x11
+#define PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT 0x12
+#define PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT 0x13
+#define PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT 0x14
+#define PCTL_STATUS__MMHUB_CONFIG_DONE_MASK 0x00000001L
+#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK 0x00000002L
+#define PCTL_STATUS__MMHUB_FENCE_REQ_MASK 0x00000004L
+#define PCTL_STATUS__MMHUB_FENCE_ACK_MASK 0x00000008L
+#define PCTL_STATUS__MMHUB_IDLE_MASK 0x00000010L
+#define PCTL_STATUS__PGFSM_CMD_STATUS_MASK 0x00000060L
+#define PCTL_STATUS__RSMU_RDTIMEOUT_CNT_MASK 0x00007F80L
+#define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR_MASK 0x00008000L
+#define PCTL_STATUS__MMHUB_POWER_MASK 0x00010000L
+#define PCTL_STATUS__RENG_RAM_STALE_MASK 0x00020000L
+#define PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK 0x00040000L
+#define PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK 0x00080000L
+#define PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK 0x00100000L
+//PCTL_PERFCOUNTER_LO
+#define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//PCTL_PERFCOUNTER_HI
+#define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//PCTL_PERFCOUNTER0_CFG
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//PCTL_PERFCOUNTER1_CFG
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//PCTL_PERFCOUNTER_RSLT_CNTL
+#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//PCTL_RESERVED_0
+#define PCTL_RESERVED_0__WORD__SHIFT 0x0
+#define PCTL_RESERVED_0__BYTE__SHIFT 0x10
+#define PCTL_RESERVED_0__BIT7__SHIFT 0x18
+#define PCTL_RESERVED_0__BIT6__SHIFT 0x19
+#define PCTL_RESERVED_0__BIT5__SHIFT 0x1a
+#define PCTL_RESERVED_0__BIT4__SHIFT 0x1b
+#define PCTL_RESERVED_0__BIT3__SHIFT 0x1c
+#define PCTL_RESERVED_0__BIT2__SHIFT 0x1d
+#define PCTL_RESERVED_0__BIT1__SHIFT 0x1e
+#define PCTL_RESERVED_0__BIT0__SHIFT 0x1f
+#define PCTL_RESERVED_0__WORD_MASK 0x0000FFFFL
+#define PCTL_RESERVED_0__BYTE_MASK 0x00FF0000L
+#define PCTL_RESERVED_0__BIT7_MASK 0x01000000L
+#define PCTL_RESERVED_0__BIT6_MASK 0x02000000L
+#define PCTL_RESERVED_0__BIT5_MASK 0x04000000L
+#define PCTL_RESERVED_0__BIT4_MASK 0x08000000L
+#define PCTL_RESERVED_0__BIT3_MASK 0x10000000L
+#define PCTL_RESERVED_0__BIT2_MASK 0x20000000L
+#define PCTL_RESERVED_0__BIT1_MASK 0x40000000L
+#define PCTL_RESERVED_0__BIT0_MASK 0x80000000L
+//PCTL_RESERVED_1
+#define PCTL_RESERVED_1__WORD__SHIFT 0x0
+#define PCTL_RESERVED_1__BYTE__SHIFT 0x10
+#define PCTL_RESERVED_1__BIT7__SHIFT 0x18
+#define PCTL_RESERVED_1__BIT6__SHIFT 0x19
+#define PCTL_RESERVED_1__BIT5__SHIFT 0x1a
+#define PCTL_RESERVED_1__BIT4__SHIFT 0x1b
+#define PCTL_RESERVED_1__BIT3__SHIFT 0x1c
+#define PCTL_RESERVED_1__BIT2__SHIFT 0x1d
+#define PCTL_RESERVED_1__BIT1__SHIFT 0x1e
+#define PCTL_RESERVED_1__BIT0__SHIFT 0x1f
+#define PCTL_RESERVED_1__WORD_MASK 0x0000FFFFL
+#define PCTL_RESERVED_1__BYTE_MASK 0x00FF0000L
+#define PCTL_RESERVED_1__BIT7_MASK 0x01000000L
+#define PCTL_RESERVED_1__BIT6_MASK 0x02000000L
+#define PCTL_RESERVED_1__BIT5_MASK 0x04000000L
+#define PCTL_RESERVED_1__BIT4_MASK 0x08000000L
+#define PCTL_RESERVED_1__BIT3_MASK 0x10000000L
+#define PCTL_RESERVED_1__BIT2_MASK 0x20000000L
+#define PCTL_RESERVED_1__BIT1_MASK 0x40000000L
+#define PCTL_RESERVED_1__BIT0_MASK 0x80000000L
+//PCTL_RESERVED_2
+#define PCTL_RESERVED_2__WORD__SHIFT 0x0
+#define PCTL_RESERVED_2__BYTE__SHIFT 0x10
+#define PCTL_RESERVED_2__BIT7__SHIFT 0x18
+#define PCTL_RESERVED_2__BIT6__SHIFT 0x19
+#define PCTL_RESERVED_2__BIT5__SHIFT 0x1a
+#define PCTL_RESERVED_2__BIT4__SHIFT 0x1b
+#define PCTL_RESERVED_2__BIT3__SHIFT 0x1c
+#define PCTL_RESERVED_2__BIT2__SHIFT 0x1d
+#define PCTL_RESERVED_2__BIT1__SHIFT 0x1e
+#define PCTL_RESERVED_2__BIT0__SHIFT 0x1f
+#define PCTL_RESERVED_2__WORD_MASK 0x0000FFFFL
+#define PCTL_RESERVED_2__BYTE_MASK 0x00FF0000L
+#define PCTL_RESERVED_2__BIT7_MASK 0x01000000L
+#define PCTL_RESERVED_2__BIT6_MASK 0x02000000L
+#define PCTL_RESERVED_2__BIT5_MASK 0x04000000L
+#define PCTL_RESERVED_2__BIT4_MASK 0x08000000L
+#define PCTL_RESERVED_2__BIT3_MASK 0x10000000L
+#define PCTL_RESERVED_2__BIT2_MASK 0x20000000L
+#define PCTL_RESERVED_2__BIT1_MASK 0x40000000L
+#define PCTL_RESERVED_2__BIT0_MASK 0x80000000L
+//PCTL_RESERVED_3
+#define PCTL_RESERVED_3__WORD__SHIFT 0x0
+#define PCTL_RESERVED_3__BYTE__SHIFT 0x10
+#define PCTL_RESERVED_3__BIT7__SHIFT 0x18
+#define PCTL_RESERVED_3__BIT6__SHIFT 0x19
+#define PCTL_RESERVED_3__BIT5__SHIFT 0x1a
+#define PCTL_RESERVED_3__BIT4__SHIFT 0x1b
+#define PCTL_RESERVED_3__BIT3__SHIFT 0x1c
+#define PCTL_RESERVED_3__BIT2__SHIFT 0x1d
+#define PCTL_RESERVED_3__BIT1__SHIFT 0x1e
+#define PCTL_RESERVED_3__BIT0__SHIFT 0x1f
+#define PCTL_RESERVED_3__WORD_MASK 0x0000FFFFL
+#define PCTL_RESERVED_3__BYTE_MASK 0x00FF0000L
+#define PCTL_RESERVED_3__BIT7_MASK 0x01000000L
+#define PCTL_RESERVED_3__BIT6_MASK 0x02000000L
+#define PCTL_RESERVED_3__BIT5_MASK 0x04000000L
+#define PCTL_RESERVED_3__BIT4_MASK 0x08000000L
+#define PCTL_RESERVED_3__BIT3_MASK 0x10000000L
+#define PCTL_RESERVED_3__BIT2_MASK 0x20000000L
+#define PCTL_RESERVED_3__BIT1_MASK 0x40000000L
+#define PCTL_RESERVED_3__BIT0_MASK 0x80000000L
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1pfdec
+//MMMC_VM_MX_L1_TLB0_STATUS
+#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2
+#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L
+//MMMC_VM_MX_L1_TLB1_STATUS
+#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2
+#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L
+//MMMC_VM_MX_L1_TLB2_STATUS
+#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2
+#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L
+//MMMC_VM_MX_L1_TLB3_STATUS
+#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2
+#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L
+//MMMC_VM_MX_L1_TLB4_STATUS
+#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2
+#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L
+//MMMC_VM_MX_L1_TLB5_STATUS
+#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2
+#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L
+//MMMC_VM_MX_L1_TLB6_STATUS
+#define MMMC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2
+#define MMMC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L
+//MMMC_VM_MX_L1_TLB7_STATUS
+#define MMMC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2
+#define MMMC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1pldec
+//MMMC_VM_MX_L1_PERFCOUNTER0_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER1_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER2_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER3_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1prdec
+//MMMC_VM_MX_L1_PERFCOUNTER_LO
+#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_PERFCOUNTER_HI
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: mmhub_l1tlb_mmvmtlspfdec
+//MMMC_VM_MX_L1_TLS0_CNTL
+#define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x4
+#define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x5
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT__SHIFT 0x6
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM__SHIFT 0x8
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP__SHIFT 0x9
+#define MMMC_VM_MX_L1_TLS0_CNTL__DEBUG_ECO_BITS__SHIFT 0x10
+#define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT_MASK 0x0000000FL
+#define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000010L
+#define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000020L
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT_MASK 0x000000C0L
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM_MASK 0x00000100L
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP_MASK 0x00000200L
+#define MMMC_VM_MX_L1_TLS0_CNTL__DEBUG_ECO_BITS_MASK 0xFFFF0000L
+//MMMC_VM_MX_L1_TLS0_CNTL0
+#define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL0__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL0__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL1
+#define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL1__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL1__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL2
+#define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL2__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL2__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL3
+#define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL3__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL3__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL4
+#define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL4__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL4__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL5
+#define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL5__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL5__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL6
+#define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL6__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL6__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL7
+#define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL7__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL7__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL8
+#define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL8__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL8__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL9
+#define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL9__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL9__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL10
+#define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL10__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL10__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL11
+#define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL11__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL11__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL12
+#define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL12__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL12__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL13
+#define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL13__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL13__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL14
+#define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL14__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL14__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL15
+#define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL15__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL15__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL16
+#define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL16__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL16__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL17
+#define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL17__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL17__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL18
+#define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL18__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL18__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL19
+#define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL19__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL19__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL20
+#define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL20__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL20__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL21
+#define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL21__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL21__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL22
+#define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL22__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL22__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL23
+#define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL23__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL23__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL24
+#define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL24__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL24__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL25
+#define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL25__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL25__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL26
+#define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL26__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL26__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL27
+#define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL27__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL27__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL28
+#define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL28__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL28__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL29
+#define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL29__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL29__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL30
+#define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL30__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL30__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL31
+#define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL31__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL31__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL32
+#define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL32__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL32__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL33
+#define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL33__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL33__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL34
+#define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL34__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL34__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL35
+#define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL35__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL35__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL36
+#define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL36__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL36__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL37
+#define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL37__EN__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE__SHIFT 0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID_MASK 0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL37__EN_MASK 0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE_MASK 0x00002000L
+//MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4_MASK 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6_MASK 0x0000003FL
+//MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6_MASK 0x0000003FL
+//MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0x000000FFL
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x001FF000L
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x01000000L
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1E000000L
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000L
+//MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+//MMVM_L2_SAW_CNTL
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
+#define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
+#define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
+#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
+#define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
+#define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
+#define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
+#define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
+#define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
+#define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a
+#define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
+#define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL
+#define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
+#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
+#define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
+#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
+#define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
+#define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
+#define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
+#define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L
+#define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0x0C000000L
+#define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000L
+//MMVM_L2_SAW_CNTL2
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
+#define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
+#define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
+#define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
+#define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
+#define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
+#define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
+#define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x03800000L
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L
+#define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L
+//MMVM_L2_SAW_CNTL3
+#define MMVM_L2_SAW_CNTL3__BANK_SELECT__SHIFT 0x0
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
+#define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
+#define MMVM_L2_SAW_CNTL3__BANK_SELECT_MASK 0x0000003FL
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
+#define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L
+//MMVM_L2_SAW_CNTL4
+#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11
+#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT 0x12
+#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x00000040L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x00000080L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x00000100L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x00000200L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x00000400L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x00000800L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x00001000L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x00002000L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x00004000L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x00008000L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x00010000L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x00020000L
+#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK 0x00040000L
+//MMVM_L2_SAW_CONTEXT0_CNTL
+#define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
+#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
+#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
+#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x1c
+#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x1d
+#define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0F000000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x10000000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x20000000L
+//MMVM_L2_SAW_CONTEXT0_CNTL2
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_L2_SAW_CONTEXTS_DISABLE
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L
+//MMVM_L2_SAW_PIPES_BUSY_LO32
+#define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32__SHIFT 0x0
+#define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32_MASK 0xFFFFFFFFL
+//MMVM_L2_SAW_PIPES_BUSY_HI32
+#define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32__SHIFT 0x0
+#define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID__SHIFT 0x3
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS_MASK 0x00000006L
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID_MASK 0x000001F8L
+//MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2dec
+//MM_ATC_L2_CNTL
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf
+#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10
+#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13
+#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14
+#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L
+#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L
+#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L
+#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L
+#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L
+//MM_ATC_L2_CNTL2
+#define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
+#define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9
+#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb
+#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc
+#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12
+#define MM_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL
+#define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L
+#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L
+#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L
+#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L
+//MM_ATC_L2_CACHE_DATA0
+#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
+#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
+#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
+#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x18
+#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L
+#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L
+#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL
+#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x0F000000L
+//MM_ATC_L2_CACHE_DATA1
+#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
+#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL
+//MM_ATC_L2_CACHE_DATA2
+#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
+#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
+//MM_ATC_L2_CNTL3
+#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0
+#define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6
+#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc
+#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12
+#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15
+#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b
+#define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e
+#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL
+#define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L
+#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L
+#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L
+#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L
+#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L
+#define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L
+//MM_ATC_L2_CNTL4
+#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0
+#define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6
+#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc
+#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL
+#define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L
+#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L
+//MM_ATC_L2_CNTL5
+#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0
+#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa
+#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL
+#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L
+//MM_ATC_L2_MM_GROUP_RT_CLASSES
+#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0
+#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL
+//MM_ATC_L2_STATUS
+#define MM_ATC_L2_STATUS__BUSY__SHIFT 0x0
+#define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT 0x1
+#define MM_ATC_L2_STATUS__BUSY_MASK 0x00000001L
+#define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK 0x00000002L
+//MM_ATC_L2_STATUS2
+#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0
+#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8
+#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL
+#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L
+//MM_ATC_L2_MISC_CG
+#define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6
+#define MM_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12
+#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MM_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L
+#define MM_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L
+#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
+//MM_ATC_L2_MEM_POWER_LS
+#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//MM_ATC_L2_CGTT_CLK_CTRL
+#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5
+#define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd
+#define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e
+#define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f
+#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL
+#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L
+#define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L
+#define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L
+#define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L
+//MM_ATC_L2_SDPPORT_CTRL
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pfdec
+//MMVM_L2_CNTL
+#define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
+#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
+#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
+#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
+#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
+#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
+#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
+#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
+#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
+#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
+#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
+#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a
+#define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
+#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
+#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL
+#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
+#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
+#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
+#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
+#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
+#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
+#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
+#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L
+#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L
+//MMVM_L2_CNTL2
+#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
+#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
+#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
+#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
+#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17
+#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
+#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
+#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
+#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
+#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
+#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
+#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L
+#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L
+#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L
+//MMVM_L2_CNTL3
+#define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
+#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
+#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
+#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
+#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
+#define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
+#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L
+#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
+#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L
+#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L
+//MMVM_L2_STATUS
+#define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0
+#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
+#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11
+#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12
+#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13
+#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14
+#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15
+#define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L
+#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL
+#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L
+#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L
+#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L
+#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L
+#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L
+//MMVM_DUMMY_PAGE_FAULT_CNTL
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL
+//MMVM_DUMMY_PAGE_FAULT_ADDR_LO32
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMVM_DUMMY_PAGE_FAULT_ADDR_HI32
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL
+//MMVM_INVALIDATE_CNTL
+#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0
+#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8
+#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL
+#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L
+//MMVM_L2_PROTECTION_FAULT_CNTL
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1
+#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5
+#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6
+#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8
+#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9
+#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb
+#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd
+#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L
+//MMVM_L2_PROTECTION_FAULT_CNTL2
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L
+//MMVM_L2_PROTECTION_FAULT_MM_CNTL3
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_MM_CNTL4
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_STATUS
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1
+#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8
+#define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9
+#define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12
+#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19
+#define MMVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT 0x1d
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL
+#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK 0x20000000L
+//MMVM_L2_PROTECTION_FAULT_ADDR_LO32
+#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_ADDR_HI32
+#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL
+//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL
+//MMVM_L2_CNTL4
+#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
+#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6
+#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7
+#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8
+#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12
+#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c
+#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d
+#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e
+#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT 0x1f
+#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL
+#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L
+#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L
+#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L
+#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L
+#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L
+#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L
+#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L
+#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK 0x80000000L
+//MMVM_L2_MM_GROUP_RT_CLASSES
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L
+//MMVM_L2_BANK_SELECT_RESERVED_CID
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L
+//MMVM_L2_BANK_SELECT_RESERVED_CID2
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L
+//MMVM_L2_CACHE_PARITY_CNTL
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L
+//MMVM_L2_CGTT_CLK_CTRL
+#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5
+#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd
+#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e
+#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f
+#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL
+#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L
+#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L
+#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L
+#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L
+//MMVM_L2_CNTL5
+#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5
+#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0xe
+#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0xf
+#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT 0x10
+#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT 0x11
+#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L
+#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00004000L
+#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00008000L
+#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK 0x00010000L
+#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK 0x00020000L
+//MMVM_L2_GCR_CNTL
+#define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0
+#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1
+#define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L
+#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL
+//MMVM_L2_CGTT_BUSY_CTRL
+#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0
+#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5
+#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL
+#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L
+//MMVM_L2_PTE_CACHE_DUMP_CNTL
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L
+//MMVM_L2_PTE_CACHE_DUMP_READ
+#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0
+#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL
+//MMVM_L2_BANK_SELECT_MASKS
+#define MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0
+#define MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4
+#define MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8
+#define MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT 0xc
+#define MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL
+#define MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L
+#define MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L
+#define MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK 0x0000F000L
+//MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC
+#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT 0x0
+#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa
+#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK 0x000003FFL
+#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK 0x00000400L
+//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT 0x0
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK 0x000003FFL
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK 0x00000400L
+//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT 0x0
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK 0x000003FFL
+#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK 0x00000400L
+//MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT
+#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT 0x0
+#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa
+#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK 0x000003FFL
+#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK 0x00000400L
+//MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ
+#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0
+#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa
+#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL
+#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK 0x00000400L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2vcdec
+//MMVM_CONTEXT0_CNTL
+#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXT1_CNTL
+#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXT2_CNTL
+#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXT3_CNTL
+#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXT4_CNTL
+#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXT5_CNTL
+#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXT6_CNTL
+#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXT7_CNTL
+#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXT8_CNTL
+#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXT9_CNTL
+#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXT10_CNTL
+#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXT11_CNTL
+#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXT12_CNTL
+#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXT13_CNTL
+#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXT14_CNTL
+#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXT15_CNTL
+#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17
+#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18
+#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L
+#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L
+//MMVM_CONTEXTS_DISABLE
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L
+//MMVM_INVALIDATE_ENG0_SEM
+#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG1_SEM
+#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG2_SEM
+#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG3_SEM
+#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG4_SEM
+#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG5_SEM
+#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG6_SEM
+#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG7_SEM
+#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG8_SEM
+#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG9_SEM
+#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG10_SEM
+#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG11_SEM
+#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG12_SEM
+#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG13_SEM
+#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG14_SEM
+#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG15_SEM
+#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG16_SEM
+#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG17_SEM
+#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG0_REQ
+#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG1_REQ
+#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG2_REQ
+#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG3_REQ
+#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG4_REQ
+#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG5_REQ
+#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG6_REQ
+#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG7_REQ
+#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG8_REQ
+#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG9_REQ
+#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG10_REQ
+#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG11_REQ
+#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG12_REQ
+#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG13_REQ
+#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG14_REQ
+#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG15_REQ
+#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG16_REQ
+#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG17_REQ
+#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG0_ACK
+#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG1_ACK
+#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG2_ACK
+#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG3_ACK
+#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG4_ACK
+#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG5_ACK
+#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG6_ACK
+#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG7_ACK
+#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG8_ACK
+#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG9_ACK
+#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG10_ACK
+#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG11_ACK
+#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG12_ACK
+#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG13_ACK
+#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG14_ACK
+#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG15_ACK
+#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG16_ACK
+#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG17_ACK
+#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+//MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pldec
+//MMMC_VM_L2_PERFCOUNTER0_CFG
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER1_CFG
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER2_CFG
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER3_CFG
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER4_CFG
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER5_CFG
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER6_CFG
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER7_CFG
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//MMUTCL2_PERFCOUNTER0_CFG
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MMUTCL2_PERFCOUNTER1_CFG
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MMUTCL2_PERFCOUNTER2_CFG
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//MMUTCL2_PERFCOUNTER3_CFG
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//MMUTCL2_PERFCOUNTER_RSLT_CNTL
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2prdec
+//MMMC_VM_L2_PERFCOUNTER_LO
+#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MMMC_VM_L2_PERFCOUNTER_HI
+#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//MMUTCL2_PERFCOUNTER_LO
+#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MMUTCL2_PERFCOUNTER_HI
+#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec
+//MMVM_PCIE_ATS_CNTL
+#define MMVM_PCIE_ATS_CNTL__STU__SHIFT 0x10
+#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
+#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
+//MMMC_VM_NB_MMIOBASE
+#define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
+#define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL
+//MMMC_VM_NB_MMIOLIMIT
+#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
+#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL
+//MMMC_VM_NB_PCI_CTRL
+#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
+#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L
+//MMMC_VM_NB_PCI_ARB
+#define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
+#define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L
+//MMMC_VM_NB_TOP_OF_DRAM_SLOT1
+#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
+#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L
+//MMMC_VM_NB_LOWER_TOP_OF_DRAM2
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L
+//MMMC_VM_NB_UPPER_TOP_OF_DRAM2
+#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
+#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL
+//MMMC_VM_FB_OFFSET
+#define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
+#define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL
+//MMMC_VM_STEERING
+#define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
+#define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L
+//MMMC_SHARED_VIRT_RESET_REQ
+#define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
+#define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//MMMC_MEM_POWER_LS
+#define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define MMMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define MMMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//MMMC_VM_CACHEABLE_DRAM_ADDRESS_START
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
+//MMMC_VM_CACHEABLE_DRAM_ADDRESS_END
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
+//MMMC_VM_LOCAL_SYSMEM_ADDRESS_START
+#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT 0x0
+#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
+//MMMC_VM_LOCAL_SYSMEM_ADDRESS_END
+#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT 0x0
+#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
+//MMMC_VM_APT_CNTL
+#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0
+#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1
+#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2
+#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x4
+#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT 0x5
+#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x6
+#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L
+#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L
+#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL
+#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000010L
+#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK 0x00000020L
+#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x000000C0L
+//MMMC_VM_LOCAL_FB_ADDRESS_START
+#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT 0x0
+#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
+//MMMC_VM_LOCAL_FB_ADDRESS_END
+#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT 0x0
+#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
+//MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL
+#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0
+#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L
+//MMUTCL2_CGTT_CLK_CTRL
+#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5
+#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd
+#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e
+#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f
+#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL
+#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L
+#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L
+#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L
+#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L
+//MMMC_SHARED_ACTIVE_FCN_ID
+#define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1e
+#define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x40000000L
+//MMUTCL2_CGTT_BUSY_CTRL
+#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0
+#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5
+#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL
+#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L
+//MMUTCL2_HARVEST_BYPASS_GROUPS
+#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0
+#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL
+//MMUTCL2_GROUP_RET_FAULT_STATUS
+#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT 0x0
+#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec
+//MMMC_VM_FB_LOCATION_BASE
+#define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
+#define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL
+//MMMC_VM_FB_LOCATION_TOP
+#define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0
+#define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL
+//MMMC_VM_AGP_TOP
+#define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
+#define MMMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL
+//MMMC_VM_AGP_BOT
+#define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
+#define MMMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL
+//MMMC_VM_AGP_BASE
+#define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
+#define MMMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_LOW_ADDR
+#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0
+#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0
+#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
+//MMMC_VM_MX_L1_TLB_CNTL
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
+#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
+#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L
+#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec
+//MM_ATC_L2_PERFCOUNTER_LO
+#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MM_ATC_L2_PERFCOUNTER_HI
+#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec
+//MM_ATC_L2_PERFCOUNTER0_CFG
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MM_ATC_L2_PERFCOUNTER1_CFG
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MM_ATC_L2_PERFCOUNTER_RSLT_CNTL
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pspdec
+//MMUTCL2_TRANSLATION_BYPASS_BY_VMID
+#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT 0x0
+#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT 0x10
+#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK 0x0000FFFFL
+#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK 0xFFFF0000L
+//MMVM_IOMMU_CONTROL_REGISTER
+#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0
+#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L
+//MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
+#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd
+#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L
+//MMUTC_TRANSLATION_FAULT_CNTL0
+#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT 0x0
+#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK 0xFFFFFFFFL
+//MMUTC_TRANSLATION_FAULT_CNTL1
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT 0x0
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT 0x4
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT 0x5
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT 0x6
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK 0x0000000FL
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK 0x00000010L
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK 0x00000020L
+#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK 0x00000040L
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpspdec
+//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT 0x0
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK 0x00000001L
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pspdec
+//MM_ATC_L2_IOV_MODE_CNTL
+#define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN__SHIFT 0x0
+#define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN_MASK 0x00000001L
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpfdec
+//MML2TLB_TLB0_STATUS
+#define MML2TLB_TLB0_STATUS__BUSY__SHIFT 0x0
+#define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2
+#define MML2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L
+#define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+#define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L
+//MML2TLB_TMZ_CNTL
+#define MML2TLB_TMZ_CNTL__TMZ_MODULATION__SHIFT 0x0
+#define MML2TLB_TMZ_CNTL__TMZ_MODULATION_MASK 0x00000001L
+//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL
+//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x8
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xc
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xd
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0xf
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x10
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x11
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x12
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1e
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00000F00L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00001000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x00006000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00008000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00010000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00020000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x07FC0000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x40000000L
+//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL
+//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x15
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x16
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT 0x18
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1f
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x001C0000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00200000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00C00000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK 0x01000000L
+#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x80000000L
+//MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ
+#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0
+#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE__SHIFT 0xa
+#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL
+#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE_MASK 0x00000400L
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpldec
+//MML2TLB_PERFCOUNTER0_CFG
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MML2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MML2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MML2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MML2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MML2TLB_PERFCOUNTER1_CFG
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MML2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MML2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MML2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MML2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MML2TLB_PERFCOUNTER2_CFG
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MML2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MML2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define MML2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define MML2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//MML2TLB_PERFCOUNTER3_CFG
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MML2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MML2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define MML2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define MML2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//MML2TLB_PERFCOUNTER_RSLT_CNTL
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbprdec
+//MML2TLB_PERFCOUNTER_LO
+#define MML2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MML2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MML2TLB_PERFCOUNTER_HI
+#define MML2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MML2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+#endif
--
2.38.1