From ab24910e55be1b68bb4fab40a4d425da771a3ca3 Mon Sep 17 00:00:00 2001
From: Fangzhi Zuo <Jerry.Zuo@amd.com>
Date: Tue, 19 Apr 2022 15:49:48 -0400
Subject: drm/amd/display: Halve DTB Clock Value for DCN32
Git-commit: 2388a778bdacad0c936dbb01048362864847f8ad
Patch-mainline: v6.0-rc1
References: jsc#PED-1166 jsc#PED-1168 jsc#PED-1170 jsc#PED-1218 jsc#PED-1220 jsc#PED-1222 jsc#PED-1223 jsc#PED-1225 jsc#PED-2849
VBIOS default clock value was halved, so the hardcoded dtb value should be
halved as well.
dtb clock should come from SMU eventually, but now dtb clock switching is not
fully supported yet in SMU.
Halve the dtb hardcoded value for now to have UHBR10 light up. Will rely on
SMU for dtb clock switching once available. The w/a is for DCN32 only, DCN321
should adopt the original value.
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 9d2d2cda5543..774de29fa532 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -599,7 +599,7 @@ void dcn32_clk_mgr_construct(
clk_mgr->dfs_ref_freq_khz = 100000;
clk_mgr->base.dprefclk_khz = 717000; /* Changed as per DCN3.2_clock_frequency doc */
- clk_mgr->dccg->ref_dtbclk_khz = 477800;
+ clk_mgr->dccg->ref_dtbclk_khz = 268750;
/* integer part is now VCO frequency in kHz */
clk_mgr->base.dentist_vco_freq_khz = 4300000;//dcn32_get_vco_frequency_from_reg(clk_mgr);
--
2.38.1