From a3215d0459917318e93e78a6fb2ae22c726720af Mon Sep 17 00:00:00 2001
From: Wenjing Liu <wenjing.liu@amd.com>
Date: Fri, 13 May 2022 11:43:45 -0400
Subject: drm/amd/display: add DP sanity checks during enable stream
Git-commit: e5309d7f66105011e0597fd55ff2ef7f636f52c6
Patch-mainline: v6.0-rc1
References: jsc#PED-1166 jsc#PED-1168 jsc#PED-1170 jsc#PED-1218 jsc#PED-1220 jsc#PED-1222 jsc#PED-1223 jsc#PED-1225 jsc#PED-2849
[why]
1. When HPD deassertion is pulled in the middle of
enabe stream link training, we will abort current training
and turn off PHY. This causes current link settings
to be zeroed this causes later stream enablement
sequence to fail as we prefer to carry on enablement
process despite of link training failure for SST.
2. When HPD is toggled after detection before before
the enable stream sequence as a result. There could be
a race condition where we could end up enable stream based
on the previous link even though the link is updated
after the HPD toggle. This causes an issue where our link
bandwidth is no longer enough to accommodate the timing
therefore causes us to oversubscribe MST payload time
slots. As discussed we decided to add basic sanity check
to make sure that our code can handle the oversubscription
failure silently without system hang.
[how]
1. Keep PHY powered on when HPD is deasserted during
enable stream and wait for the detection sequence to power
it off later.
2. Do not allocate payload if the required timeslot for
current timing is greater than 64 timeslots.
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 2 ++
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 16 +++++++++++-----
drivers/gpu/drm/amd/display/dc/inc/core_status.h | 2 +-
4 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 72376075db0c..283957dbdf93 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -422,6 +422,8 @@ char *dc_status_to_str(enum dc_status status)
return "The value specified is not supported.";
case DC_NO_LINK_ENC_RESOURCE:
return "No link encoder resource";
+ case DC_FAIL_DP_PAYLOAD_ALLOCATION:
+ return "Fail dp payload allocation";
case DC_ERROR_UNEXPECTED:
return "Unexpected error";
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 38a458141791..ab9655d6e5c8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3597,6 +3597,7 @@ static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx,
"allocation table for "
"pipe idx: %d\n",
pipe_ctx->pipe_idx);
+ return DC_FAIL_DP_PAYLOAD_ALLOCATION;
}
proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 927826a1c358..65d6d6d2b782 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2875,10 +2875,13 @@ bool perform_link_training_with_retries(
fail_count++;
dp_trace_lt_fail_count_update(link, fail_count, false);
- /* latest link training still fail, skip delay and keep PHY on
- */
- if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
- break;
+ if (link->ep_type == DISPLAY_ENDPOINT_PHY) {
+ /* latest link training still fail or link training is aborted
+ * skip delay and keep PHY on
+ */
+ if (j == (attempts - 1) || (status == LINK_TRAINING_ABORT))
+ break;
+ }
DC_LOG_WARNING("%s: Link training attempt %u of %d failed @ rate(%d) x lane(%d)\n",
__func__, (unsigned int)j + 1, attempts, cur_link_settings.link_rate,
@@ -6890,6 +6893,10 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table(
if (allocate) {
avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
+ /// Validation should filter out modes that exceed link BW
+ ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT);
+ if (req_slot_count > MAX_MTP_SLOT_COUNT)
+ return false;
} else {
/// Leave req_slot_count = 0 if allocate is false.
}
@@ -6917,7 +6924,6 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table(
&start_time_slot,
1);
- ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); /// Validation should filter out modes that exceed link BW
core_link_write_dpcd(
link,
DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
index 444182a97e6e..8eb8d4afa876 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
@@ -54,7 +54,7 @@ enum dc_status {
DC_UNSUPPORTED_VALUE = 25,
DC_NO_LINK_ENC_RESOURCE = 26,
-
+ DC_FAIL_DP_PAYLOAD_ALLOCATION = 27,
DC_ERROR_UNEXPECTED = -1
};
--
2.38.1