From 393b5c570fe9bdabde5de4d8d6169220bec0ddeb Mon Sep 17 00:00:00 2001
From: Wenjing Liu <wenjing.liu@amd.com>
Date: Thu, 26 May 2022 15:52:42 -0400
Subject: drm/amd/display: lower lane count first when CR done partially fails
in EQ
Git-commit: c443514a7d6d648bc497efbe502e2a49738b94de
Patch-mainline: v6.0-rc1
References: jsc#PED-1166 jsc#PED-1168 jsc#PED-1170 jsc#PED-1218 jsc#PED-1220 jsc#PED-1222 jsc#PED-1223 jsc#PED-1225 jsc#PED-2849
[why]
According to DP specs, in EQ DONE phase of link training, we
should lower lane count when at least one CR DONE bit is set to 1, while
lower link rate when all CR DONE bits are 0s. However in our code, we will
treat both cases as latter. This is not exactly correct based on the specs
expectation.
[how]
Check lane0 CR DONE bit when it is still set but CR DONE fails,
we treat it as a partial CR DONE failure in EQ DONE phase, we
will follow the same fallback flow as when ED DONE fails in EQ
DONE phase.
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 13 +++++++------
.../drm/amd/display/include/link_service_types.h | 2 ++
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index d745b2198fe4..013498f2ec0f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1326,7 +1326,9 @@ static enum link_training_result perform_channel_equalization_sequence(
/* 5. check CR done*/
if (!dp_is_cr_done(lane_count, dpcd_lane_status))
- return LINK_TRAINING_EQ_FAIL_CR;
+ return dpcd_lane_status[0].bits.CR_DONE_0 ?
+ LINK_TRAINING_EQ_FAIL_CR_PARTIAL :
+ LINK_TRAINING_EQ_FAIL_CR;
/* 6. check CHEQ done*/
if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
@@ -1882,6 +1884,9 @@ static void print_status_message(
case LINK_TRAINING_EQ_FAIL_CR:
lt_result = "CR failed in EQ";
break;
+ case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
+ lt_result = "CR failed in EQ partially";
+ break;
case LINK_TRAINING_EQ_FAIL_EQ:
lt_result = "EQ failed";
break;
@@ -3612,11 +3617,6 @@ static bool decide_fallback_link_setting(
struct dc_link_settings *cur,
enum link_training_result training_result)
{
- if (!cur)
- return false;
- if (!max)
- return false;
-
if (dp_get_link_encoding_format(max) == DP_128b_132b_ENCODING ||
link->dc->debug.force_dp2_lt_fallback_method)
return decide_fallback_link_setting_max_bw_policy(link, max, cur,
@@ -3646,6 +3646,7 @@ static bool decide_fallback_link_setting(
break;
}
case LINK_TRAINING_EQ_FAIL_EQ:
+ case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
{
if (!reached_minimum_lane_count(cur->lane_count)) {
cur->lane_count = reduce_lane_count(cur->lane_count);
diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 447a56286dd0..23f7d7354aaa 100644
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -67,6 +67,8 @@ enum link_training_result {
LINK_TRAINING_CR_FAIL_LANE23,
/* CR DONE bit is cleared during EQ step */
LINK_TRAINING_EQ_FAIL_CR,
+ /* CR DONE bit is cleared but LANE0_CR_DONE is set during EQ step */
+ LINK_TRAINING_EQ_FAIL_CR_PARTIAL,
/* other failure during EQ step */
LINK_TRAINING_EQ_FAIL_EQ,
LINK_TRAINING_LQA_FAIL,
--
2.38.1