From 78160683c8530e88ca7853d832cf8d1135fcdcad Mon Sep 17 00:00:00 2001
From: Imre Deak <imre.deak@intel.com>
Date: Fri, 15 Apr 2022 00:06:54 +0300
Subject: drm/i915: Remove the aliasing of power domain enum values
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Git-commit: c97bbab02ad7d174b50541864bfa45cf1e4ee14f
Patch-mainline: v5.19-rc1
References: jsc#PED-1166 jsc#PED-1168 jsc#PED-1170 jsc#PED-1218 jsc#PED-1220 jsc#PED-1222 jsc#PED-1223 jsc#PED-1225
Aliasing the intel_display_power_domain enum values was required because
of the u64 power domain mask size limit. This makes the dmesg/debugfs
printouts of the domain names somewhat unclear, for instance domain
names for port D are shown on D12+ platforms where the corresponding
port is called TC1. Make this clearer by removing the aliasing which is
possible after a previous patch converting the mask to a bitmap.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220414210657.1785773-15-imre.deak@intel.com
Acked-by: Patrik Jakobsson <pjakobsson@suse.de>
---
.../drm/i915/display/intel_display_power.c | 84 +++++++++++++------
.../drm/i915/display/intel_display_power.h | 26 ++----
2 files changed, 67 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index b417ca4e5c58..f1f4d877a975 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -80,12 +80,22 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_LANES_E";
case POWER_DOMAIN_PORT_DDI_LANES_F:
return "PORT_DDI_LANES_F";
- case POWER_DOMAIN_PORT_DDI_LANES_G:
- return "PORT_DDI_LANES_G";
- case POWER_DOMAIN_PORT_DDI_LANES_H:
- return "PORT_DDI_LANES_H";
- case POWER_DOMAIN_PORT_DDI_LANES_I:
- return "PORT_DDI_LANES_I";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC1:
+ return "PORT_DDI_LANES_TC1";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC2:
+ return "PORT_DDI_LANES_TC2";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC3:
+ return "PORT_DDI_LANES_TC3";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC4:
+ return "PORT_DDI_LANES_TC4";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC5:
+ return "PORT_DDI_LANES_TC5";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC6:
+ return "PORT_DDI_LANES_TC6";
+ case POWER_DOMAIN_PORT_DDI_LANES_D_XELPD:
+ return "PORT_DDI_LANES_D_XELPD";
+ case POWER_DOMAIN_PORT_DDI_LANES_E_XELPD:
+ return "PORT_DDI_LANES_E_XELPD";
case POWER_DOMAIN_PORT_DDI_IO_A:
return "PORT_DDI_IO_A";
case POWER_DOMAIN_PORT_DDI_IO_B:
@@ -98,12 +108,22 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_IO_E";
case POWER_DOMAIN_PORT_DDI_IO_F:
return "PORT_DDI_IO_F";
- case POWER_DOMAIN_PORT_DDI_IO_G:
- return "PORT_DDI_IO_G";
- case POWER_DOMAIN_PORT_DDI_IO_H:
- return "PORT_DDI_IO_H";
- case POWER_DOMAIN_PORT_DDI_IO_I:
- return "PORT_DDI_IO_I";
+ case POWER_DOMAIN_PORT_DDI_IO_TC1:
+ return "PORT_DDI_IO_TC1";
+ case POWER_DOMAIN_PORT_DDI_IO_TC2:
+ return "PORT_DDI_IO_TC2";
+ case POWER_DOMAIN_PORT_DDI_IO_TC3:
+ return "PORT_DDI_IO_TC3";
+ case POWER_DOMAIN_PORT_DDI_IO_TC4:
+ return "PORT_DDI_IO_TC4";
+ case POWER_DOMAIN_PORT_DDI_IO_TC5:
+ return "PORT_DDI_IO_TC5";
+ case POWER_DOMAIN_PORT_DDI_IO_TC6:
+ return "PORT_DDI_IO_TC6";
+ case POWER_DOMAIN_PORT_DDI_IO_D_XELPD:
+ return "PORT_DDI_IO_D_XELPD";
+ case POWER_DOMAIN_PORT_DDI_IO_E_XELPD:
+ return "PORT_DDI_IO_E_XELPD";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
@@ -128,12 +148,22 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_E";
case POWER_DOMAIN_AUX_F:
return "AUX_F";
- case POWER_DOMAIN_AUX_G:
- return "AUX_G";
- case POWER_DOMAIN_AUX_H:
- return "AUX_H";
- case POWER_DOMAIN_AUX_I:
- return "AUX_I";
+ case POWER_DOMAIN_AUX_USBC1:
+ return "AUX_USBC1";
+ case POWER_DOMAIN_AUX_USBC2:
+ return "AUX_USBC2";
+ case POWER_DOMAIN_AUX_USBC3:
+ return "AUX_USBC3";
+ case POWER_DOMAIN_AUX_USBC4:
+ return "AUX_USBC4";
+ case POWER_DOMAIN_AUX_USBC5:
+ return "AUX_USBC5";
+ case POWER_DOMAIN_AUX_USBC6:
+ return "AUX_USBC6";
+ case POWER_DOMAIN_AUX_D_XELPD:
+ return "AUX_D_XELPD";
+ case POWER_DOMAIN_AUX_E_XELPD:
+ return "AUX_E_XELPD";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
case POWER_DOMAIN_AUX_TBT_C:
@@ -144,12 +174,18 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_TBT_E";
case POWER_DOMAIN_AUX_TBT_F:
return "AUX_TBT_F";
- case POWER_DOMAIN_AUX_TBT_G:
- return "AUX_TBT_G";
- case POWER_DOMAIN_AUX_TBT_H:
- return "AUX_TBT_H";
- case POWER_DOMAIN_AUX_TBT_I:
- return "AUX_TBT_I";
+ case POWER_DOMAIN_AUX_TBT1:
+ return "AUX_TBT1";
+ case POWER_DOMAIN_AUX_TBT2:
+ return "AUX_TBT2";
+ case POWER_DOMAIN_AUX_TBT3:
+ return "AUX_TBT3";
+ case POWER_DOMAIN_AUX_TBT4:
+ return "AUX_TBT4";
+ case POWER_DOMAIN_AUX_TBT5:
+ return "AUX_TBT5";
+ case POWER_DOMAIN_AUX_TBT6:
+ return "AUX_TBT6";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
case POWER_DOMAIN_INIT:
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 2ea30a4cfaa8..b58c5bada6d8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -48,18 +48,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_LANES_D,
POWER_DOMAIN_PORT_DDI_LANES_E,
POWER_DOMAIN_PORT_DDI_LANES_F,
- POWER_DOMAIN_PORT_DDI_LANES_G,
- POWER_DOMAIN_PORT_DDI_LANES_H,
- POWER_DOMAIN_PORT_DDI_LANES_I,
- POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_LANES_D, /* tgl+ */
+ POWER_DOMAIN_PORT_DDI_LANES_TC1,
POWER_DOMAIN_PORT_DDI_LANES_TC2,
POWER_DOMAIN_PORT_DDI_LANES_TC3,
POWER_DOMAIN_PORT_DDI_LANES_TC4,
POWER_DOMAIN_PORT_DDI_LANES_TC5,
POWER_DOMAIN_PORT_DDI_LANES_TC6,
- POWER_DOMAIN_PORT_DDI_LANES_D_XELPD = POWER_DOMAIN_PORT_DDI_LANES_TC5, /* XELPD */
+ POWER_DOMAIN_PORT_DDI_LANES_D_XELPD,
POWER_DOMAIN_PORT_DDI_LANES_E_XELPD,
POWER_DOMAIN_PORT_DDI_IO_A,
@@ -68,18 +65,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_IO_D,
POWER_DOMAIN_PORT_DDI_IO_E,
POWER_DOMAIN_PORT_DDI_IO_F,
- POWER_DOMAIN_PORT_DDI_IO_G,
- POWER_DOMAIN_PORT_DDI_IO_H,
- POWER_DOMAIN_PORT_DDI_IO_I,
- POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_IO_D, /* tgl+ */
+ POWER_DOMAIN_PORT_DDI_IO_TC1,
POWER_DOMAIN_PORT_DDI_IO_TC2,
POWER_DOMAIN_PORT_DDI_IO_TC3,
POWER_DOMAIN_PORT_DDI_IO_TC4,
POWER_DOMAIN_PORT_DDI_IO_TC5,
POWER_DOMAIN_PORT_DDI_IO_TC6,
- POWER_DOMAIN_PORT_DDI_IO_D_XELPD = POWER_DOMAIN_PORT_DDI_IO_TC5, /* XELPD */
+ POWER_DOMAIN_PORT_DDI_IO_D_XELPD,
POWER_DOMAIN_PORT_DDI_IO_E_XELPD,
POWER_DOMAIN_PORT_DSI,
@@ -94,18 +88,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_D,
POWER_DOMAIN_AUX_E,
POWER_DOMAIN_AUX_F,
- POWER_DOMAIN_AUX_G,
- POWER_DOMAIN_AUX_H,
- POWER_DOMAIN_AUX_I,
- POWER_DOMAIN_AUX_USBC1 = POWER_DOMAIN_AUX_D, /* tgl+ */
+ POWER_DOMAIN_AUX_USBC1,
POWER_DOMAIN_AUX_USBC2,
POWER_DOMAIN_AUX_USBC3,
POWER_DOMAIN_AUX_USBC4,
POWER_DOMAIN_AUX_USBC5,
POWER_DOMAIN_AUX_USBC6,
- POWER_DOMAIN_AUX_D_XELPD = POWER_DOMAIN_AUX_USBC5, /* XELPD */
+ POWER_DOMAIN_AUX_D_XELPD,
POWER_DOMAIN_AUX_E_XELPD,
POWER_DOMAIN_AUX_IO_A,
@@ -113,11 +104,8 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_TBT_D,
POWER_DOMAIN_AUX_TBT_E,
POWER_DOMAIN_AUX_TBT_F,
- POWER_DOMAIN_AUX_TBT_G,
- POWER_DOMAIN_AUX_TBT_H,
- POWER_DOMAIN_AUX_TBT_I,
- POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_TBT_D, /* tgl+ */
+ POWER_DOMAIN_AUX_TBT1,
POWER_DOMAIN_AUX_TBT2,
POWER_DOMAIN_AUX_TBT3,
POWER_DOMAIN_AUX_TBT4,
--
2.38.1