From 20cf16547d86306aee16daec5e7d559f9df812a1 Mon Sep 17 00:00:00 2001
From: Chris Park <Chris.Park@amd.com>
Date: Fri, 4 Feb 2022 17:03:24 -0500
Subject: drm/amd/display: OVT Update on InfoFrame and Mode Management
Git-commit: 427a60c1c30e1c0e9d0800a63df51985aaf3a26a
Patch-mainline: v6.0-rc1
References: jsc#PED-1166 jsc#PED-1168 jsc#PED-1170 jsc#PED-1218 jsc#PED-1220 jsc#PED-1222 jsc#PED-1223 jsc#PED-1225 jsc#PED-2849
[Why]
Integrate OVT timing from DM to DC logic to update info frame
and mode management to report the resolution to the OS.
[How]
Reflect RID and Frame Rate to AVI InfoFrame Version 5.
Define new Timing Standard for OVT timing.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Chris Park <Chris.Park@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Patrik Jakobsson <pjakobsson@suse.de>
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 11 +++++++++++
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 ++
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 ++
drivers/gpu/drm/amd/display/include/set_mode_types.h | 8 ++++++--
4 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 30087f118f79..4d39ae38826c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2515,6 +2515,8 @@ static void set_avi_info_frame(
union hdmi_info_packet hdmi_info;
union display_content_support support = {0};
unsigned int vic = pipe_ctx->stream->timing.vic;
+ unsigned int rid = pipe_ctx->stream->timing.rid;
+ unsigned int fr_ind = pipe_ctx->stream->timing.fr_index;
enum dc_timing_3d_format format;
memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
@@ -2707,6 +2709,15 @@ static void set_avi_info_frame(
hdmi_info.bits.header.length = 14;
}
+ if (rid != 0 && fr_ind != 0) {
+ hdmi_info.bits.header.version = 5;
+ hdmi_info.bits.header.length = 15;
+
+ hdmi_info.bits.FR0_FR3 = fr_ind & 0xF;
+ hdmi_info.bits.FR4 = (fr_ind >> 4) & 0x1;
+ hdmi_info.bits.RID0_RID5 = rid;
+ }
+
/* pixel repetition
* PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
* repetition start from 1 */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index d75416dc9fae..584aaf6967fd 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -784,6 +784,8 @@ struct dc_crtc_timing {
uint32_t vic;
uint32_t hdmi_vic;
+ uint32_t rid;
+ uint32_t fr_index;
enum dc_timing_3d_format timing_3d_format;
enum dc_color_depth display_color_depth;
enum dc_pixel_encoding pixel_encoding;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 084074a23031..7e595310a4b8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -280,6 +280,8 @@ enum dc_timing_source {
TIMING_SOURCE_EDID_CEA_SVD,
TIMING_SOURCE_EDID_CVT_3BYTE,
TIMING_SOURCE_EDID_4BYTE,
+ TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB,
+ TIMING_SOURCE_EDID_CEA_RID,
TIMING_SOURCE_VBIOS,
TIMING_SOURCE_CV,
TIMING_SOURCE_TV,
diff --git a/drivers/gpu/drm/amd/display/include/set_mode_types.h b/drivers/gpu/drm/amd/display/include/set_mode_types.h
index 845fea8a387f..75f2c79492c0 100644
--- a/drivers/gpu/drm/amd/display/include/set_mode_types.h
+++ b/drivers/gpu/drm/amd/display/include/set_mode_types.h
@@ -84,10 +84,14 @@ union hdmi_info_packet {
uint16_t bar_left;
uint16_t bar_right;
- uint8_t F140_F143:4;
+ uint8_t FR0_FR3:4;
uint8_t ACE0_ACE3:4;
- uint8_t reserved[13];
+ uint8_t RID0_RID5:6;
+ uint8_t FR4:1;
+ uint8_t F157:1;
+
+ uint8_t reserved[12];
} bits;
struct info_packet_raw_data packet_raw_data;
--
2.38.1