From: Sasha Neftin <sasha.neftin@intel.com>
Date: Thu, 24 Jun 2021 11:19:08 +0300
Subject: e1000e: Additional PHY power saving in S0ix
Patch-mainline: v5.15-rc1
Git-commit: 3ad3e28cb203309fb29022dea41cd65df0583632
References: jsc#SLE-18382
After transferring the MAC-PHY interface to the SMBus set the PHY
to S0ix low power idle mode.
Suggested-by: Dima Ruinskiy <dima.ruinskiy@intel.com>
Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Dvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
---
drivers/net/ethernet/intel/e1000e/netdev.c | 6 ++++++
1 file changed, 6 insertions(+)
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -6378,10 +6378,16 @@ static void e1000e_s0ix_entry_flow(struc
ew32(CTRL_EXT, mac_data);
/* DFT control: PHY bit: page769_20[0] = 1
+ * page769_20[7] - PHY PLL stop
+ * page769_20[8] - PHY go to the electrical idle
+ * page769_20[9] - PHY serdes disable
* Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
*/
e1e_rphy(hw, I82579_DFT_CTRL, &phy_data);
phy_data |= BIT(0);
+ phy_data |= BIT(7);
+ phy_data |= BIT(8);
+ phy_data |= BIT(9);
e1e_wphy(hw, I82579_DFT_CTRL, phy_data);
mac_data = er32(EXTCNF_CTRL);