From: Yevgeny Kliteynik <kliteyn@nvidia.com>
Date: Sun, 4 Jul 2021 20:43:10 +0300
Subject: net/mlx5: DR, Remove HW specific STE type from nic domain
Patch-mainline: v5.15-rc1
Git-commit: 46f2a8ae8a7008f845b537ba800faf0f1f1f86e7
References: jsc#SLE-19253
Instead of using the HW specific STEv0 type, it is better to use
an enum to indicate if this is an RX or TX nic domain.
This means that now we will need to convert the nic domain type
to the corresponding STE type.
Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
---
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c | 14 +--
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_domain.c | 8 -
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c | 2
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c | 8 -
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c | 10 +-
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h | 2
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c | 45 ++++++----
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c | 2
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h | 9 +-
drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h | 6 -
10 files changed, 61 insertions(+), 45 deletions(-)
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c
@@ -434,7 +434,7 @@ dr_action_reformat_to_action_type(enum m
* the new size of the STEs array, rule with actions.
*/
static void dr_actions_apply(struct mlx5dr_domain *dmn,
- enum mlx5dr_ste_entry_type ste_type,
+ enum mlx5dr_domain_nic_type nic_type,
u8 *action_type_set,
u8 *last_ste,
struct mlx5dr_ste_actions_attr *attr,
@@ -443,7 +443,7 @@ static void dr_actions_apply(struct mlx5
struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx;
u32 added_stes = 0;
- if (ste_type == MLX5DR_STE_TYPE_RX)
+ if (nic_type == DR_DOMAIN_NIC_TYPE_RX)
mlx5dr_ste_set_actions_rx(ste_ctx, dmn, action_type_set,
last_ste, attr, &added_stes);
else
@@ -455,7 +455,7 @@ static void dr_actions_apply(struct mlx5
static enum dr_action_domain
dr_action_get_action_domain(enum mlx5dr_domain_type domain,
- enum mlx5dr_ste_entry_type ste_type)
+ enum mlx5dr_domain_nic_type nic_type)
{
switch (domain) {
case MLX5DR_DOMAIN_TYPE_NIC_RX:
@@ -463,7 +463,7 @@ dr_action_get_action_domain(enum mlx5dr_
case MLX5DR_DOMAIN_TYPE_NIC_TX:
return DR_ACTION_DOMAIN_NIC_EGRESS;
case MLX5DR_DOMAIN_TYPE_FDB:
- if (ste_type == MLX5DR_STE_TYPE_RX)
+ if (nic_type == DR_DOMAIN_NIC_TYPE_RX)
return DR_ACTION_DOMAIN_FDB_INGRESS;
return DR_ACTION_DOMAIN_FDB_EGRESS;
default:
@@ -551,7 +551,7 @@ int mlx5dr_actions_build_ste_arr(struct
u32 *new_hw_ste_arr_sz)
{
struct mlx5dr_domain_rx_tx *nic_dmn = nic_matcher->nic_tbl->nic_dmn;
- bool rx_rule = nic_dmn->ste_type == MLX5DR_STE_TYPE_RX;
+ bool rx_rule = nic_dmn->type == DR_DOMAIN_NIC_TYPE_RX;
struct mlx5dr_domain *dmn = matcher->tbl->dmn;
u8 action_type_set[DR_ACTION_TYP_MAX] = {};
struct mlx5dr_ste_actions_attr attr = {};
@@ -565,7 +565,7 @@ int mlx5dr_actions_build_ste_arr(struct
attr.gvmi = dmn->info.caps.gvmi;
attr.hit_gvmi = dmn->info.caps.gvmi;
attr.final_icm_addr = nic_dmn->default_icm_addr;
- action_domain = dr_action_get_action_domain(dmn->type, nic_dmn->ste_type);
+ action_domain = dr_action_get_action_domain(dmn->type, nic_dmn->type);
for (i = 0; i < num_actions; i++) {
struct mlx5dr_action_dest_tbl *dest_tbl;
@@ -752,7 +752,7 @@ int mlx5dr_actions_build_ste_arr(struct
}
dr_actions_apply(dmn,
- nic_dmn->ste_type,
+ nic_dmn->type,
action_type_set,
last_ste,
&attr,
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_domain.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_domain.c
@@ -245,7 +245,7 @@ static int dr_domain_caps_init(struct ml
return -ENOTSUPP;
dmn->info.supp_sw_steering = true;
- dmn->info.rx.ste_type = MLX5DR_STE_TYPE_RX;
+ dmn->info.rx.type = DR_DOMAIN_NIC_TYPE_RX;
dmn->info.rx.default_icm_addr = dmn->info.caps.nic_rx_drop_address;
dmn->info.rx.drop_icm_addr = dmn->info.caps.nic_rx_drop_address;
break;
@@ -254,7 +254,7 @@ static int dr_domain_caps_init(struct ml
return -ENOTSUPP;
dmn->info.supp_sw_steering = true;
- dmn->info.tx.ste_type = MLX5DR_STE_TYPE_TX;
+ dmn->info.tx.type = DR_DOMAIN_NIC_TYPE_TX;
dmn->info.tx.default_icm_addr = dmn->info.caps.nic_tx_allow_address;
dmn->info.tx.drop_icm_addr = dmn->info.caps.nic_tx_drop_address;
break;
@@ -265,8 +265,8 @@ static int dr_domain_caps_init(struct ml
if (!DR_DOMAIN_SW_STEERING_SUPPORTED(dmn, fdb))
return -ENOTSUPP;
- dmn->info.rx.ste_type = MLX5DR_STE_TYPE_RX;
- dmn->info.tx.ste_type = MLX5DR_STE_TYPE_TX;
+ dmn->info.rx.type = DR_DOMAIN_NIC_TYPE_RX;
+ dmn->info.tx.type = DR_DOMAIN_NIC_TYPE_TX;
vport_cap = mlx5dr_get_vport_cap(&dmn->info.caps, 0);
if (!vport_cap) {
mlx5dr_err(dmn, "Failed to get esw manager vport\n");
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c
@@ -403,7 +403,7 @@ static int dr_matcher_set_ste_builders(s
int ret, i;
sb = nic_matcher->ste_builder_arr[outer_ipv][inner_ipv];
- rx = nic_dmn->ste_type == MLX5DR_STE_TYPE_RX;
+ rx = nic_dmn->type == DR_DOMAIN_NIC_TYPE_RX;
/* Create a temporary mask to track and clear used mask fields */
if (matcher->match_criteria & DR_MATCHER_CRITERIA_OUTER)
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c
@@ -404,7 +404,7 @@ dr_rule_rehash_htbl(struct mlx5dr_rule *
info.miss_icm_addr = nic_matcher->e_anchor->chunk->icm_addr;
mlx5dr_ste_set_formatted_ste(dmn->ste_ctx,
dmn->info.caps.gvmi,
- nic_dmn,
+ nic_dmn->type,
new_htbl,
formatted_ste,
&info);
@@ -1015,12 +1015,12 @@ static enum mlx5dr_ipv dr_rule_get_ipv(s
}
static bool dr_rule_skip(enum mlx5dr_domain_type domain,
- enum mlx5dr_ste_entry_type ste_type,
+ enum mlx5dr_domain_nic_type nic_type,
struct mlx5dr_match_param *mask,
struct mlx5dr_match_param *value,
u32 flow_source)
{
- bool rx = ste_type == MLX5DR_STE_TYPE_RX;
+ bool rx = nic_type == DR_DOMAIN_NIC_TYPE_RX;
if (domain != MLX5DR_DOMAIN_TYPE_FDB)
return false;
@@ -1067,7 +1067,7 @@ dr_rule_create_rule_nic(struct mlx5dr_ru
INIT_LIST_HEAD(&nic_rule->rule_members_list);
- if (dr_rule_skip(dmn->type, nic_dmn->ste_type, &matcher->mask, param,
+ if (dr_rule_skip(dmn->type, nic_dmn->type, &matcher->mask, param,
rule->flow_source))
return 0;
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c
@@ -382,14 +382,15 @@ void mlx5dr_ste_prepare_for_postsend(str
/* Init one ste as a pattern for ste data array */
void mlx5dr_ste_set_formatted_ste(struct mlx5dr_ste_ctx *ste_ctx,
u16 gvmi,
- struct mlx5dr_domain_rx_tx *nic_dmn,
+ enum mlx5dr_domain_nic_type nic_type,
struct mlx5dr_ste_htbl *htbl,
u8 *formatted_ste,
struct mlx5dr_htbl_connect_info *connect_info)
{
+ bool is_rx = nic_type == DR_DOMAIN_NIC_TYPE_RX;
struct mlx5dr_ste ste = {};
- ste_ctx->ste_init(formatted_ste, htbl->lu_type, nic_dmn->ste_type, gvmi);
+ ste_ctx->ste_init(formatted_ste, htbl->lu_type, is_rx, gvmi);
ste.hw_ste = formatted_ste;
if (connect_info->type == CONNECT_HIT)
@@ -408,7 +409,7 @@ int mlx5dr_ste_htbl_init_and_postsend(st
mlx5dr_ste_set_formatted_ste(dmn->ste_ctx,
dmn->info.caps.gvmi,
- nic_dmn,
+ nic_dmn->type,
htbl,
formatted_ste,
connect_info);
@@ -649,6 +650,7 @@ int mlx5dr_ste_build_ste_arr(struct mlx5
u8 *ste_arr)
{
struct mlx5dr_domain_rx_tx *nic_dmn = nic_matcher->nic_tbl->nic_dmn;
+ bool is_rx = nic_dmn->type == DR_DOMAIN_NIC_TYPE_RX;
struct mlx5dr_domain *dmn = matcher->tbl->dmn;
struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx;
struct mlx5dr_ste_build *sb;
@@ -663,7 +665,7 @@ int mlx5dr_ste_build_ste_arr(struct mlx5
for (i = 0; i < nic_matcher->num_of_builders; i++) {
ste_ctx->ste_init(ste_arr,
sb->lu_type,
- nic_dmn->ste_type,
+ is_rx,
dmn->info.caps.gvmi);
mlx5dr_ste_set_bit_mask(ste_arr, sb->bit_mask);
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h
@@ -146,7 +146,7 @@ struct mlx5dr_ste_ctx {
/* Getters and Setters */
void (*ste_init)(u8 *hw_ste_p, u16 lu_type,
- u8 entry_type, u16 gvmi);
+ bool is_rx, u16 gvmi);
void (*set_next_lu_type)(u8 *hw_ste_p, u16 lu_type);
u16 (*get_next_lu_type)(u8 *hw_ste_p);
void (*set_miss_addr)(u8 *hw_ste_p, u64 miss_addr);
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c
@@ -8,6 +8,12 @@
#define SVLAN_ETHERTYPE 0x88a8
#define DR_STE_ENABLE_FLOW_TAG BIT(31)
+enum dr_ste_v0_entry_type {
+ DR_STE_TYPE_TX = 1,
+ DR_STE_TYPE_RX = 2,
+ DR_STE_TYPE_MODIFY_PKT = 6,
+};
+
enum dr_ste_v0_action_tunl {
DR_STE_TUNL_ACTION_NONE = 0,
DR_STE_TUNL_ACTION_ENABLE = 1,
@@ -292,8 +298,8 @@ static void dr_ste_v0_set_hit_addr(u8 *h
MLX5_SET(ste_general, hw_ste_p, next_table_base_31_5_size, index);
}
-static void dr_ste_v0_init(u8 *hw_ste_p, u16 lu_type,
- u8 entry_type, u16 gvmi)
+static void dr_ste_v0_init_full(u8 *hw_ste_p, u16 lu_type,
+ enum dr_ste_v0_entry_type entry_type, u16 gvmi)
{
dr_ste_v0_set_entry_type(hw_ste_p, entry_type);
dr_ste_v0_set_lu_type(hw_ste_p, lu_type);
@@ -307,6 +313,15 @@ static void dr_ste_v0_init(u8 *hw_ste_p,
MLX5_SET(ste_rx_steering_mult, hw_ste_p, miss_address_63_48, gvmi);
}
+static void dr_ste_v0_init(u8 *hw_ste_p, u16 lu_type,
+ bool is_rx, u16 gvmi)
+{
+ enum dr_ste_v0_entry_type entry_type;
+
+ entry_type = is_rx ? DR_STE_TYPE_RX : DR_STE_TYPE_TX;
+ dr_ste_v0_init_full(hw_ste_p, lu_type, entry_type, gvmi);
+}
+
static void dr_ste_v0_rx_set_flow_tag(u8 *hw_ste_p, u32 flow_tag)
{
MLX5_SET(ste_rx_steering_mult, hw_ste_p, qp_list_pointer,
@@ -380,13 +395,13 @@ static void dr_ste_v0_set_rewrite_action
static void dr_ste_v0_arr_init_next(u8 **last_ste,
u32 *added_stes,
- enum mlx5dr_ste_entry_type entry_type,
+ enum dr_ste_v0_entry_type entry_type,
u16 gvmi)
{
(*added_stes)++;
*last_ste += DR_STE_SIZE;
- dr_ste_v0_init(*last_ste, MLX5DR_STE_LU_TYPE_DONT_CARE,
- entry_type, gvmi);
+ dr_ste_v0_init_full(*last_ste, MLX5DR_STE_LU_TYPE_DONT_CARE,
+ entry_type, gvmi);
}
static void
@@ -404,7 +419,7 @@ dr_ste_v0_set_actions_tx(struct mlx5dr_d
* modify headers for outer headers only
*/
if (action_type_set[DR_ACTION_TYP_MODIFY_HDR]) {
- dr_ste_v0_set_entry_type(last_ste, MLX5DR_STE_TYPE_MODIFY_PKT);
+ dr_ste_v0_set_entry_type(last_ste, DR_STE_TYPE_MODIFY_PKT);
dr_ste_v0_set_rewrite_actions(last_ste,
attr->modify_actions,
attr->modify_index);
@@ -417,7 +432,7 @@ dr_ste_v0_set_actions_tx(struct mlx5dr_d
if (i || action_type_set[DR_ACTION_TYP_MODIFY_HDR])
dr_ste_v0_arr_init_next(&last_ste,
added_stes,
- MLX5DR_STE_TYPE_TX,
+ DR_STE_TYPE_TX,
attr->gvmi);
dr_ste_v0_set_tx_push_vlan(last_ste,
@@ -435,7 +450,7 @@ dr_ste_v0_set_actions_tx(struct mlx5dr_d
action_type_set[DR_ACTION_TYP_PUSH_VLAN])
dr_ste_v0_arr_init_next(&last_ste,
added_stes,
- MLX5DR_STE_TYPE_TX,
+ DR_STE_TYPE_TX,
attr->gvmi);
dr_ste_v0_set_tx_encap(last_ste,
@@ -469,7 +484,7 @@ dr_ste_v0_set_actions_rx(struct mlx5dr_d
dr_ste_v0_set_counter_id(last_ste, attr->ctr_id);
if (action_type_set[DR_ACTION_TYP_TNL_L3_TO_L2]) {
- dr_ste_v0_set_entry_type(last_ste, MLX5DR_STE_TYPE_MODIFY_PKT);
+ dr_ste_v0_set_entry_type(last_ste, DR_STE_TYPE_MODIFY_PKT);
dr_ste_v0_set_rx_decap_l3(last_ste, attr->decap_with_vlan);
dr_ste_v0_set_rewrite_actions(last_ste,
attr->decap_actions,
@@ -488,7 +503,7 @@ dr_ste_v0_set_actions_rx(struct mlx5dr_d
action_type_set[DR_ACTION_TYP_TNL_L3_TO_L2])
dr_ste_v0_arr_init_next(&last_ste,
added_stes,
- MLX5DR_STE_TYPE_RX,
+ DR_STE_TYPE_RX,
attr->gvmi);
dr_ste_v0_set_rx_pop_vlan(last_ste);
@@ -496,13 +511,13 @@ dr_ste_v0_set_actions_rx(struct mlx5dr_d
}
if (action_type_set[DR_ACTION_TYP_MODIFY_HDR]) {
- if (dr_ste_v0_get_entry_type(last_ste) == MLX5DR_STE_TYPE_MODIFY_PKT)
+ if (dr_ste_v0_get_entry_type(last_ste) == DR_STE_TYPE_MODIFY_PKT)
dr_ste_v0_arr_init_next(&last_ste,
added_stes,
- MLX5DR_STE_TYPE_MODIFY_PKT,
+ DR_STE_TYPE_MODIFY_PKT,
attr->gvmi);
else
- dr_ste_v0_set_entry_type(last_ste, MLX5DR_STE_TYPE_MODIFY_PKT);
+ dr_ste_v0_set_entry_type(last_ste, DR_STE_TYPE_MODIFY_PKT);
dr_ste_v0_set_rewrite_actions(last_ste,
attr->modify_actions,
@@ -510,10 +525,10 @@ dr_ste_v0_set_actions_rx(struct mlx5dr_d
}
if (action_type_set[DR_ACTION_TYP_TAG]) {
- if (dr_ste_v0_get_entry_type(last_ste) == MLX5DR_STE_TYPE_MODIFY_PKT)
+ if (dr_ste_v0_get_entry_type(last_ste) == DR_STE_TYPE_MODIFY_PKT)
dr_ste_v0_arr_init_next(&last_ste,
added_stes,
- MLX5DR_STE_TYPE_RX,
+ DR_STE_TYPE_RX,
attr->gvmi);
dr_ste_v0_rx_set_flow_tag(last_ste, attr->flow_tag);
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c
@@ -322,7 +322,7 @@ static void dr_ste_v1_set_hit_addr(u8 *h
}
static void dr_ste_v1_init(u8 *hw_ste_p, u16 lu_type,
- u8 entry_type, u16 gvmi)
+ bool is_rx, u16 gvmi)
{
dr_ste_v1_set_lu_type(hw_ste_p, lu_type);
dr_ste_v1_set_next_lu_type(hw_ste_p, MLX5DR_STE_LU_TYPE_DONT_CARE);
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h
@@ -804,10 +804,15 @@ struct mlx5dr_cmd_caps {
u8 isolate_vl_tc:1;
};
+enum mlx5dr_domain_nic_type {
+ DR_DOMAIN_NIC_TYPE_RX,
+ DR_DOMAIN_NIC_TYPE_TX,
+};
+
struct mlx5dr_domain_rx_tx {
u64 drop_icm_addr;
u64 default_icm_addr;
- enum mlx5dr_ste_entry_type ste_type;
+ enum mlx5dr_domain_nic_type type;
struct mutex mutex; /* protect rx/tx domain */
};
@@ -1216,7 +1221,7 @@ int mlx5dr_ste_htbl_init_and_postsend(st
bool update_hw_ste);
void mlx5dr_ste_set_formatted_ste(struct mlx5dr_ste_ctx *ste_ctx,
u16 gvmi,
- struct mlx5dr_domain_rx_tx *nic_dmn,
+ enum mlx5dr_domain_nic_type nic_type,
struct mlx5dr_ste_htbl *htbl,
u8 *formatted_ste,
struct mlx5dr_htbl_connect_info *connect_info);
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h
@@ -8,12 +8,6 @@ enum {
MLX5DR_STE_LU_TYPE_DONT_CARE = 0x0f,
};
-enum mlx5dr_ste_entry_type {
- MLX5DR_STE_TYPE_TX = 1,
- MLX5DR_STE_TYPE_RX = 2,
- MLX5DR_STE_TYPE_MODIFY_PKT = 6,
-};
-
struct mlx5_ifc_ste_general_bits {
u8 entry_type[0x4];
u8 reserved_at_4[0x4];